Lines Matching refs:getOptLevel
279 if (getOptLevel() <= EnableGlobalISelAtO) { in AArch64TargetMachine()
340 if (TM.getOptLevel() != CodeGenOpt::None) in AArch64PassConfig()
408 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) in addIRPasses()
415 if (TM->getOptLevel() != CodeGenOpt::None) { in addIRPasses()
425 if (TM->getOptLevel() != CodeGenOpt::None) { in addIRPasses()
430 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { in addIRPasses()
448 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant) in addPreISel()
453 if ((TM->getOptLevel() != CodeGenOpt::None && in addPreISel()
456 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && in addPreISel()
465 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel())); in addInstSelector()
470 getOptLevel() != CodeGenOpt::None) in addInstSelector()
497 if (TM->getOptLevel() == CodeGenOpt::None) in addPreGlobalInstructionSelect()
525 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination) in addPreRegAlloc()
529 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) { in addPreRegAlloc()
539 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) in addPostRegAlloc()
542 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc()) in addPostRegAlloc()
551 if (TM->getOptLevel() != CodeGenOpt::None) { in addPreSched2()
563 if (TM->getOptLevel() != CodeGenOpt::None) { in addPreSched2()
573 if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt) in addPreEmitPass()
586 if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables) in addPreEmitPass()
589 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH && in addPreEmitPass()