188   bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
507   MachineInstr *DefiningMI;  in optimizeLdStInterleave()  local
520       DefiningMI = MRI->getUniqueVRegDef(SeqReg);  in optimizeLdStInterleave()
522       if (!processSeqRegInst(DefiningMI, StReg, StRegKill, NumReg))  in optimizeLdStInterleave()
632 bool AArch64SIMDInstrOpt::processSeqRegInst(MachineInstr *DefiningMI,  in processSeqRegInst()  argument
634   assert (DefiningMI != NULL);  in processSeqRegInst()
635   if (DefiningMI->getOpcode() != AArch64::REG_SEQUENCE)  in processSeqRegInst()
639     StReg[i]     = DefiningMI->getOperand(2*i+1).getReg();  in processSeqRegInst()
640     StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill());  in processSeqRegInst()
643     if (DefiningMI->getOperand(2*i+2).isImm()) {  in processSeqRegInst()
644       switch (DefiningMI->getOperand(2*i+2).getImm()) {  in processSeqRegInst()