44 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()
45   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegs()
46   if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows())  in getCalleeSavedRegs()
48   if (MF->getFunction().getCallingConv() == CallingConv::GHC)  in getCalleeSavedRegs()
52   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)  in getCalleeSavedRegs()
54   if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)  in getCalleeSavedRegs()
56   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)  in getCalleeSavedRegs()
57     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?  in getCalleeSavedRegs()
60   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()  in getCalleeSavedRegs()
62       MF->getFunction().getAttributes().hasAttrSomewhere(  in getCalleeSavedRegs()
65   if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)  in getCalleeSavedRegs()
72     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()
73   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegsViaCopy()
74   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&  in getCalleeSavedRegsViaCopy()
75       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())  in getCalleeSavedRegsViaCopy()
81     MachineFunction &MF) const {  in UpdateCustomCalleeSavedRegs()
82   const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);  in UpdateCustomCalleeSavedRegs()
88     if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {  in UpdateCustomCalleeSavedRegs()
94   MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);  in UpdateCustomCalleeSavedRegs()
111 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,  in getCallPreservedMask()  argument
113   bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);  in getCallPreservedMask()
124   if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()  in getCallPreservedMask()
126       MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))  in getCallPreservedMask()
144 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF,  in UpdateCustomCallPreservedMask()  argument
146   uint32_t *UpdatedMask = MF.allocateRegMask();  in UpdateCustomCallPreservedMask()
151     if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {  in UpdateCustomCallPreservedMask()
169 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,  in getThisReturnPreservedMask()  argument
187 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()
188   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getReservedRegs()
195   if (TFI->hasFP(MF) || TT.isOSDarwin())  in getReservedRegs()
199     if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))  in getReservedRegs()
203   if (hasBasePointer(MF))  in getReservedRegs()
207   if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))  in getReservedRegs()
214 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,  in isReservedReg()  argument
216   return getReservedRegs(MF)[Reg];  in isReservedReg()
219 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {  in isAnyArgRegReserved()
225                      [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});  in isAnyArgRegReserved()
229     const MachineFunction &MF) const {  in emitReservedArgRegCallError()
230   const Function &F = MF.getFunction();  in emitReservedArgRegCallError()
235 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,  in isAsmClobberable()  argument
237   return !isReservedReg(MF, PhysReg);  in isAsmClobberable()
245 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,  in getPointerRegClass()  argument
259 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()
260   const MachineFrameInfo &MFI = MF.getFrameInfo();  in hasBasePointer()
270   if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {  in hasBasePointer()
271     if (needsStackRealignment(MF))  in hasBasePointer()
287 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()
288   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getFrameRegister()
289   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;  in getFrameRegister()
293     const MachineFunction &MF) const {  in requiresRegisterScavenging()
298     const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()
303 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {  in useFPForScavengingIndex()
309   const AArch64FrameLowering &TFI = *getFrameLowering(MF);  in useFPForScavengingIndex()
310   return TFI.hasFP(MF);  in useFPForScavengingIndex()
314     const MachineFunction &MF) const {  in requiresFrameIndexScavenging()
319 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()
320   const MachineFrameInfo &MFI = MF.getFrameInfo();  in cannotEliminateFrame()
321   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())  in cannotEliminateFrame()
353   MachineFunction &MF = *MI->getParent()->getParent();  in needsFrameBaseReg()  local
354   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in needsFrameBaseReg()
355   MachineFrameInfo &MFI = MF.getFrameInfo();  in needsFrameBaseReg()
375   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))  in needsFrameBaseReg()
409   const MachineFunction &MF = *MBB->getParent();  in materializeFrameBaseRegister()  local
411       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in materializeFrameBaseRegister()
414   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));  in materializeFrameBaseRegister()
432   const MachineFunction *MF = MI.getParent()->getParent();  in resolveFrameIndex()  local
434       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();  in resolveFrameIndex()
447   MachineFunction &MF = *MBB.getParent();  in eliminateFrameIndex()  local
449       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in eliminateFrameIndex()
450   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in eliminateFrameIndex()
459     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,  in eliminateFrameIndex()
468   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);  in eliminateFrameIndex()
486       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);  in eliminateFrameIndex()
492                                                   MachineFunction &MF) const {  in getRegPressureLimit()
493   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getRegPressureLimit()
507               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP  in getRegPressureLimit()
508               - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved()  in getRegPressureLimit()
509               - hasBasePointer(MF);  // X19  in getRegPressureLimit()