Lines Matching refs:MVT
117 static const MVT MVT_CC = MVT::i32;
130 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
131 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
134 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
135 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
136 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
137 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
141 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
142 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
144 addDRTypeForNEON(MVT::v2f32); in AArch64TargetLowering()
145 addDRTypeForNEON(MVT::v8i8); in AArch64TargetLowering()
146 addDRTypeForNEON(MVT::v4i16); in AArch64TargetLowering()
147 addDRTypeForNEON(MVT::v2i32); in AArch64TargetLowering()
148 addDRTypeForNEON(MVT::v1i64); in AArch64TargetLowering()
149 addDRTypeForNEON(MVT::v1f64); in AArch64TargetLowering()
150 addDRTypeForNEON(MVT::v4f16); in AArch64TargetLowering()
152 addQRTypeForNEON(MVT::v4f32); in AArch64TargetLowering()
153 addQRTypeForNEON(MVT::v2f64); in AArch64TargetLowering()
154 addQRTypeForNEON(MVT::v16i8); in AArch64TargetLowering()
155 addQRTypeForNEON(MVT::v8i16); in AArch64TargetLowering()
156 addQRTypeForNEON(MVT::v4i32); in AArch64TargetLowering()
157 addQRTypeForNEON(MVT::v2i64); in AArch64TargetLowering()
158 addQRTypeForNEON(MVT::v8f16); in AArch64TargetLowering()
165 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
166 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in AArch64TargetLowering()
167 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
168 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
169 setOperationAction(ISD::SETCC, MVT::f16, Custom); in AArch64TargetLowering()
170 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
171 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
172 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in AArch64TargetLowering()
173 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in AArch64TargetLowering()
174 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AArch64TargetLowering()
175 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
176 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
177 setOperationAction(ISD::BR_CC, MVT::f16, Custom); in AArch64TargetLowering()
178 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
179 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in AArch64TargetLowering()
180 setOperationAction(ISD::SELECT, MVT::i32, Custom); in AArch64TargetLowering()
181 setOperationAction(ISD::SELECT, MVT::i64, Custom); in AArch64TargetLowering()
182 setOperationAction(ISD::SELECT, MVT::f16, Custom); in AArch64TargetLowering()
183 setOperationAction(ISD::SELECT, MVT::f32, Custom); in AArch64TargetLowering()
184 setOperationAction(ISD::SELECT, MVT::f64, Custom); in AArch64TargetLowering()
185 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
186 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
187 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); in AArch64TargetLowering()
188 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
189 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
190 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in AArch64TargetLowering()
191 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in AArch64TargetLowering()
193 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in AArch64TargetLowering()
194 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in AArch64TargetLowering()
195 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in AArch64TargetLowering()
197 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
198 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
199 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering()
201 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in AArch64TargetLowering()
205 setOperationAction(ISD::XOR, MVT::i32, Custom); in AArch64TargetLowering()
206 setOperationAction(ISD::XOR, MVT::i64, Custom); in AArch64TargetLowering()
210 setOperationAction(ISD::FABS, MVT::f128, Expand); in AArch64TargetLowering()
211 setOperationAction(ISD::FADD, MVT::f128, Custom); in AArch64TargetLowering()
212 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
213 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
214 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
215 setOperationAction(ISD::FMA, MVT::f128, Expand); in AArch64TargetLowering()
216 setOperationAction(ISD::FMUL, MVT::f128, Custom); in AArch64TargetLowering()
217 setOperationAction(ISD::FNEG, MVT::f128, Expand); in AArch64TargetLowering()
218 setOperationAction(ISD::FPOW, MVT::f128, Expand); in AArch64TargetLowering()
219 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
220 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
221 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
222 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
223 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
224 setOperationAction(ISD::FSUB, MVT::f128, Custom); in AArch64TargetLowering()
225 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); in AArch64TargetLowering()
226 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
227 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in AArch64TargetLowering()
228 setOperationAction(ISD::SELECT, MVT::f128, Custom); in AArch64TargetLowering()
229 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
230 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
235 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
236 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
237 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in AArch64TargetLowering()
238 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AArch64TargetLowering()
239 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); in AArch64TargetLowering()
240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
241 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
242 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
243 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
244 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
245 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
246 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
247 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
250 setOperationAction(ISD::VASTART, MVT::Other, Custom); in AArch64TargetLowering()
251 setOperationAction(ISD::VAARG, MVT::Other, Custom); in AArch64TargetLowering()
252 setOperationAction(ISD::VACOPY, MVT::Other, Custom); in AArch64TargetLowering()
253 setOperationAction(ISD::VAEND, MVT::Other, Expand); in AArch64TargetLowering()
256 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AArch64TargetLowering()
257 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AArch64TargetLowering()
260 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in AArch64TargetLowering()
262 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); in AArch64TargetLowering()
265 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in AArch64TargetLowering()
268 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in AArch64TargetLowering()
271 setOperationAction(ISD::ADDC, MVT::i32, Custom); in AArch64TargetLowering()
272 setOperationAction(ISD::ADDE, MVT::i32, Custom); in AArch64TargetLowering()
273 setOperationAction(ISD::SUBC, MVT::i32, Custom); in AArch64TargetLowering()
274 setOperationAction(ISD::SUBE, MVT::i32, Custom); in AArch64TargetLowering()
275 setOperationAction(ISD::ADDC, MVT::i64, Custom); in AArch64TargetLowering()
276 setOperationAction(ISD::ADDE, MVT::i64, Custom); in AArch64TargetLowering()
277 setOperationAction(ISD::SUBC, MVT::i64, Custom); in AArch64TargetLowering()
278 setOperationAction(ISD::SUBE, MVT::i64, Custom); in AArch64TargetLowering()
281 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AArch64TargetLowering()
282 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AArch64TargetLowering()
283 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering()
289 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in AArch64TargetLowering()
290 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in AArch64TargetLowering()
292 setOperationAction(ISD::CTPOP, MVT::i32, Custom); in AArch64TargetLowering()
293 setOperationAction(ISD::CTPOP, MVT::i64, Custom); in AArch64TargetLowering()
295 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
296 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
297 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering()
301 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
302 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
303 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
304 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
305 setOperationAction(ISD::UREM, MVT::i32, Expand); in AArch64TargetLowering()
306 setOperationAction(ISD::UREM, MVT::i64, Expand); in AArch64TargetLowering()
309 setOperationAction(ISD::SADDO, MVT::i32, Custom); in AArch64TargetLowering()
310 setOperationAction(ISD::SADDO, MVT::i64, Custom); in AArch64TargetLowering()
311 setOperationAction(ISD::UADDO, MVT::i32, Custom); in AArch64TargetLowering()
312 setOperationAction(ISD::UADDO, MVT::i64, Custom); in AArch64TargetLowering()
313 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in AArch64TargetLowering()
314 setOperationAction(ISD::SSUBO, MVT::i64, Custom); in AArch64TargetLowering()
315 setOperationAction(ISD::USUBO, MVT::i32, Custom); in AArch64TargetLowering()
316 setOperationAction(ISD::USUBO, MVT::i64, Custom); in AArch64TargetLowering()
317 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
318 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
319 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
320 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
322 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
323 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
324 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
325 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
326 setOperationAction(ISD::FPOW, MVT::f32, Expand); in AArch64TargetLowering()
327 setOperationAction(ISD::FPOW, MVT::f64, Expand); in AArch64TargetLowering()
328 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in AArch64TargetLowering()
329 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in AArch64TargetLowering()
331 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in AArch64TargetLowering()
333 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in AArch64TargetLowering()
335 setOperationAction(ISD::FREM, MVT::f16, Promote); in AArch64TargetLowering()
336 setOperationAction(ISD::FREM, MVT::v4f16, Expand); in AArch64TargetLowering()
337 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering()
338 setOperationAction(ISD::FPOW, MVT::f16, Promote); in AArch64TargetLowering()
339 setOperationAction(ISD::FPOW, MVT::v4f16, Expand); in AArch64TargetLowering()
340 setOperationAction(ISD::FPOW, MVT::v8f16, Expand); in AArch64TargetLowering()
341 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in AArch64TargetLowering()
342 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand); in AArch64TargetLowering()
343 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand); in AArch64TargetLowering()
344 setOperationAction(ISD::FCOS, MVT::f16, Promote); in AArch64TargetLowering()
345 setOperationAction(ISD::FCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
346 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
347 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
348 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
349 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
350 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
351 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
352 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
353 setOperationAction(ISD::FEXP, MVT::f16, Promote); in AArch64TargetLowering()
354 setOperationAction(ISD::FEXP, MVT::v4f16, Expand); in AArch64TargetLowering()
355 setOperationAction(ISD::FEXP, MVT::v8f16, Expand); in AArch64TargetLowering()
356 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in AArch64TargetLowering()
357 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand); in AArch64TargetLowering()
358 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); in AArch64TargetLowering()
359 setOperationAction(ISD::FLOG, MVT::f16, Promote); in AArch64TargetLowering()
360 setOperationAction(ISD::FLOG, MVT::v4f16, Expand); in AArch64TargetLowering()
361 setOperationAction(ISD::FLOG, MVT::v8f16, Expand); in AArch64TargetLowering()
362 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in AArch64TargetLowering()
363 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand); in AArch64TargetLowering()
364 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand); in AArch64TargetLowering()
365 setOperationAction(ISD::FLOG10, MVT::f16, Promote); in AArch64TargetLowering()
366 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand); in AArch64TargetLowering()
367 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand); in AArch64TargetLowering()
370 setOperationAction(ISD::SELECT, MVT::f16, Promote); in AArch64TargetLowering()
371 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in AArch64TargetLowering()
372 setOperationAction(ISD::SETCC, MVT::f16, Promote); in AArch64TargetLowering()
373 setOperationAction(ISD::BR_CC, MVT::f16, Promote); in AArch64TargetLowering()
374 setOperationAction(ISD::FADD, MVT::f16, Promote); in AArch64TargetLowering()
375 setOperationAction(ISD::FSUB, MVT::f16, Promote); in AArch64TargetLowering()
376 setOperationAction(ISD::FMUL, MVT::f16, Promote); in AArch64TargetLowering()
377 setOperationAction(ISD::FDIV, MVT::f16, Promote); in AArch64TargetLowering()
378 setOperationAction(ISD::FMA, MVT::f16, Promote); in AArch64TargetLowering()
379 setOperationAction(ISD::FNEG, MVT::f16, Promote); in AArch64TargetLowering()
380 setOperationAction(ISD::FABS, MVT::f16, Promote); in AArch64TargetLowering()
381 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in AArch64TargetLowering()
382 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
383 setOperationAction(ISD::FFLOOR, MVT::f16, Promote); in AArch64TargetLowering()
384 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in AArch64TargetLowering()
385 setOperationAction(ISD::FRINT, MVT::f16, Promote); in AArch64TargetLowering()
386 setOperationAction(ISD::FROUND, MVT::f16, Promote); in AArch64TargetLowering()
387 setOperationAction(ISD::FTRUNC, MVT::f16, Promote); in AArch64TargetLowering()
388 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
389 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering()
390 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); in AArch64TargetLowering()
391 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote); in AArch64TargetLowering()
394 setOperationAction(ISD::FADD, MVT::v4f16, Promote); in AArch64TargetLowering()
395 setOperationAction(ISD::FSUB, MVT::v4f16, Promote); in AArch64TargetLowering()
396 setOperationAction(ISD::FMUL, MVT::v4f16, Promote); in AArch64TargetLowering()
397 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
398 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
399 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
400 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
401 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
402 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
403 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
404 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
405 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
407 setOperationAction(ISD::FABS, MVT::v4f16, Expand); in AArch64TargetLowering()
408 setOperationAction(ISD::FNEG, MVT::v4f16, Expand); in AArch64TargetLowering()
409 setOperationAction(ISD::FROUND, MVT::v4f16, Expand); in AArch64TargetLowering()
410 setOperationAction(ISD::FMA, MVT::v4f16, Expand); in AArch64TargetLowering()
411 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); in AArch64TargetLowering()
412 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
413 setOperationAction(ISD::SELECT, MVT::v4f16, Expand); in AArch64TargetLowering()
414 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
415 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand); in AArch64TargetLowering()
416 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand); in AArch64TargetLowering()
417 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand); in AArch64TargetLowering()
418 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); in AArch64TargetLowering()
419 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); in AArch64TargetLowering()
420 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); in AArch64TargetLowering()
421 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
423 setOperationAction(ISD::FABS, MVT::v8f16, Expand); in AArch64TargetLowering()
424 setOperationAction(ISD::FADD, MVT::v8f16, Expand); in AArch64TargetLowering()
425 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
426 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering()
427 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
428 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand); in AArch64TargetLowering()
429 setOperationAction(ISD::FMA, MVT::v8f16, Expand); in AArch64TargetLowering()
430 setOperationAction(ISD::FMUL, MVT::v8f16, Expand); in AArch64TargetLowering()
431 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); in AArch64TargetLowering()
432 setOperationAction(ISD::FNEG, MVT::v8f16, Expand); in AArch64TargetLowering()
433 setOperationAction(ISD::FROUND, MVT::v8f16, Expand); in AArch64TargetLowering()
434 setOperationAction(ISD::FRINT, MVT::v8f16, Expand); in AArch64TargetLowering()
435 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
436 setOperationAction(ISD::FSUB, MVT::v8f16, Expand); in AArch64TargetLowering()
437 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand); in AArch64TargetLowering()
438 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); in AArch64TargetLowering()
439 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
440 setOperationAction(ISD::SELECT, MVT::v8f16, Expand); in AArch64TargetLowering()
441 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
442 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
446 for (MVT Ty : {MVT::f32, MVT::f64}) { in AArch64TargetLowering()
460 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal); in AArch64TargetLowering()
461 setOperationAction(ISD::FFLOOR, MVT::f16, Legal); in AArch64TargetLowering()
462 setOperationAction(ISD::FCEIL, MVT::f16, Legal); in AArch64TargetLowering()
463 setOperationAction(ISD::FRINT, MVT::f16, Legal); in AArch64TargetLowering()
464 setOperationAction(ISD::FTRUNC, MVT::f16, Legal); in AArch64TargetLowering()
465 setOperationAction(ISD::FROUND, MVT::f16, Legal); in AArch64TargetLowering()
466 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in AArch64TargetLowering()
467 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in AArch64TargetLowering()
468 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); in AArch64TargetLowering()
469 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); in AArch64TargetLowering()
472 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in AArch64TargetLowering()
474 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in AArch64TargetLowering()
476 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); in AArch64TargetLowering()
477 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); in AArch64TargetLowering()
478 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); in AArch64TargetLowering()
479 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom); in AArch64TargetLowering()
480 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); in AArch64TargetLowering()
485 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); in AArch64TargetLowering()
490 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
491 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
493 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
494 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
500 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AArch64TargetLowering()
501 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AArch64TargetLowering()
506 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering()
507 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
508 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
509 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
510 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
512 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering()
513 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand); in AArch64TargetLowering()
515 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in AArch64TargetLowering()
516 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in AArch64TargetLowering()
517 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in AArch64TargetLowering()
518 setTruncStoreAction(MVT::f128, MVT::f80, Expand); in AArch64TargetLowering()
519 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in AArch64TargetLowering()
520 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in AArch64TargetLowering()
521 setTruncStoreAction(MVT::f128, MVT::f16, Expand); in AArch64TargetLowering()
523 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in AArch64TargetLowering()
524 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in AArch64TargetLowering()
529 setIndexedLoadAction(im, MVT::i8, Legal); in AArch64TargetLowering()
530 setIndexedLoadAction(im, MVT::i16, Legal); in AArch64TargetLowering()
531 setIndexedLoadAction(im, MVT::i32, Legal); in AArch64TargetLowering()
532 setIndexedLoadAction(im, MVT::i64, Legal); in AArch64TargetLowering()
533 setIndexedLoadAction(im, MVT::f64, Legal); in AArch64TargetLowering()
534 setIndexedLoadAction(im, MVT::f32, Legal); in AArch64TargetLowering()
535 setIndexedLoadAction(im, MVT::f16, Legal); in AArch64TargetLowering()
536 setIndexedStoreAction(im, MVT::i8, Legal); in AArch64TargetLowering()
537 setIndexedStoreAction(im, MVT::i16, Legal); in AArch64TargetLowering()
538 setIndexedStoreAction(im, MVT::i32, Legal); in AArch64TargetLowering()
539 setIndexedStoreAction(im, MVT::i64, Legal); in AArch64TargetLowering()
540 setIndexedStoreAction(im, MVT::f64, Legal); in AArch64TargetLowering()
541 setIndexedStoreAction(im, MVT::f32, Legal); in AArch64TargetLowering()
542 setIndexedStoreAction(im, MVT::f16, Legal); in AArch64TargetLowering()
546 setOperationAction(ISD::TRAP, MVT::Other, Legal); in AArch64TargetLowering()
618 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AArch64TargetLowering()
623 setOperationAction(ISD::FABS, MVT::v1f64, Expand); in AArch64TargetLowering()
624 setOperationAction(ISD::FADD, MVT::v1f64, Expand); in AArch64TargetLowering()
625 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
626 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
627 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
628 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
629 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); in AArch64TargetLowering()
630 setOperationAction(ISD::FMA, MVT::v1f64, Expand); in AArch64TargetLowering()
631 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); in AArch64TargetLowering()
632 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand); in AArch64TargetLowering()
633 setOperationAction(ISD::FNEG, MVT::v1f64, Expand); in AArch64TargetLowering()
634 setOperationAction(ISD::FPOW, MVT::v1f64, Expand); in AArch64TargetLowering()
635 setOperationAction(ISD::FREM, MVT::v1f64, Expand); in AArch64TargetLowering()
636 setOperationAction(ISD::FROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
637 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); in AArch64TargetLowering()
638 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
639 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
640 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
641 setOperationAction(ISD::FSUB, MVT::v1f64, Expand); in AArch64TargetLowering()
642 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand); in AArch64TargetLowering()
643 setOperationAction(ISD::SETCC, MVT::v1f64, Expand); in AArch64TargetLowering()
644 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
645 setOperationAction(ISD::SELECT, MVT::v1f64, Expand); in AArch64TargetLowering()
646 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
647 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
649 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
650 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); in AArch64TargetLowering()
651 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
652 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
653 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
655 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in AArch64TargetLowering()
659 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32); in AArch64TargetLowering()
660 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32); in AArch64TargetLowering()
661 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32); in AArch64TargetLowering()
662 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32); in AArch64TargetLowering()
665 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32); in AArch64TargetLowering()
666 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32); in AArch64TargetLowering()
667 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i16, MVT::v8i32); in AArch64TargetLowering()
668 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i16, MVT::v8i32); in AArch64TargetLowering()
670 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
671 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
672 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); in AArch64TargetLowering()
673 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom); in AArch64TargetLowering()
676 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); in AArch64TargetLowering()
677 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom); in AArch64TargetLowering()
679 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in AArch64TargetLowering()
680 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); in AArch64TargetLowering()
682 setOperationAction(ISD::CTTZ, MVT::v2i8, Expand); in AArch64TargetLowering()
683 setOperationAction(ISD::CTTZ, MVT::v4i16, Expand); in AArch64TargetLowering()
684 setOperationAction(ISD::CTTZ, MVT::v2i32, Expand); in AArch64TargetLowering()
685 setOperationAction(ISD::CTTZ, MVT::v1i64, Expand); in AArch64TargetLowering()
686 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand); in AArch64TargetLowering()
687 setOperationAction(ISD::CTTZ, MVT::v8i16, Expand); in AArch64TargetLowering()
688 setOperationAction(ISD::CTTZ, MVT::v4i32, Expand); in AArch64TargetLowering()
689 setOperationAction(ISD::CTTZ, MVT::v2i64, Expand); in AArch64TargetLowering()
692 setOperationAction(ISD::MUL, MVT::v2i64, Expand); in AArch64TargetLowering()
694 setOperationAction(ISD::MUL, MVT::v8i16, Custom); in AArch64TargetLowering()
695 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in AArch64TargetLowering()
696 setOperationAction(ISD::MUL, MVT::v2i64, Custom); in AArch64TargetLowering()
699 for (MVT VT : MVT::integer_valuetypes()) { in AArch64TargetLowering()
706 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering()
711 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); in AArch64TargetLowering()
712 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); in AArch64TargetLowering()
715 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering()
718 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { in AArch64TargetLowering()
730 for (MVT InnerVT : MVT::vector_valuetypes()) { in AArch64TargetLowering()
739 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) { in AArch64TargetLowering()
748 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom); in AArch64TargetLowering()
754 void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) { in addTypeForNEON()
758 MVT PromoteTo = EVT(VT).changeVectorElementTypeToInteger().getSimpleVT(); in addTypeForNEON()
764 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { in addTypeForNEON()
794 for (MVT InnerVT : MVT::all_valuetypes()) in addTypeForNEON()
798 if (VT != MVT::v8i8 && VT != MVT::v16i8) in addTypeForNEON()
814 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
820 (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16())) in addTypeForNEON()
834 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
836 addTypeForNEON(VT, MVT::v2i32); in addDRTypeForNEON()
839 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
841 addTypeForNEON(VT, MVT::v4i32); in addQRTypeForNEON()
847 return MVT::i32; in getSetCCResultType()
1032 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode()
1034 if (VT == MVT::v8i8 || VT == MVT::v16i8) { in computeKnownBitsForTargetNode()
1038 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { in computeKnownBitsForTargetNode()
1050 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL, in getScalarShiftAmountTy()
1052 return MVT::i64; in getScalarShiftAmountTy()
1075 VT == MVT::v2i64; in allowsMisalignedMemoryAccesses()
1506 assert(VT != MVT::f128); in emitComparison()
1507 if (VT == MVT::f16 && !FullFP16) { in emitComparison()
1508 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1509 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1510 VT = MVT::f32; in emitComparison()
1607 assert(LHS.getValueType() != MVT::f128); in emitConditionalComparison()
1608 if (LHS.getValueType() == MVT::f16 && !FullFP16) { in emitConditionalComparison()
1609 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1610 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1627 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32); in emitConditionalComparison()
1652 if (Val->getOperand(0).getValueType() == MVT::f128) in canEmitConjunction()
1860 if ((VT == MVT::i32 && Shift <= 31) || (VT == MVT::i64 && Shift <= 63)) in getCmpOperandFoldingProfit()
1880 if ((VT == MVT::i32 && C != 0x80000000 && in getAArch64Cmp()
1882 (VT == MVT::i64 && C != 0x80000000ULL && in getAArch64Cmp()
1885 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; in getAArch64Cmp()
1891 if ((VT == MVT::i32 && C != 0 && in getAArch64Cmp()
1893 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) { in getAArch64Cmp()
1895 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; in getAArch64Cmp()
1901 if ((VT == MVT::i32 && C != INT32_MAX && in getAArch64Cmp()
1903 (VT == MVT::i64 && C != INT64_MAX && in getAArch64Cmp()
1906 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; in getAArch64Cmp()
1912 if ((VT == MVT::i32 && C != UINT32_MAX && in getAArch64Cmp()
1914 (VT == MVT::i64 && C != UINT64_MAX && in getAArch64Cmp()
1917 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; in getAArch64Cmp()
1968 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 && in getAArch64Cmp()
1974 DAG.getValueType(MVT::i16)); in getAArch64Cmp()
2000 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && in getAArch64XALUOOp()
2031 if (Op.getValueType() == MVT::i32) { in getAArch64XALUOOp()
2037 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); in getAArch64XALUOOp()
2038 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); in getAArch64XALUOOp()
2039 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2040 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, in getAArch64XALUOOp()
2041 DAG.getConstant(0, DL, MVT::i64)); in getAArch64XALUOOp()
2046 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); in getAArch64XALUOOp()
2053 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add, in getAArch64XALUOOp()
2054 DAG.getConstant(32, DL, MVT::i64)); in getAArch64XALUOOp()
2055 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits); in getAArch64XALUOOp()
2056 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value, in getAArch64XALUOOp()
2057 DAG.getConstant(31, DL, MVT::i64)); in getAArch64XALUOOp()
2060 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32); in getAArch64XALUOOp()
2069 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, in getAArch64XALUOOp()
2070 DAG.getConstant(32, DL, MVT::i64)); in getAArch64XALUOOp()
2071 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp()
2074 DAG.getConstant(0, DL, MVT::i64), in getAArch64XALUOOp()
2079 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type"); in getAArch64XALUOOp()
2081 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2083 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2084 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value, in getAArch64XALUOOp()
2085 DAG.getConstant(63, DL, MVT::i64)); in getAArch64XALUOOp()
2088 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp()
2092 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2093 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp()
2096 DAG.getConstant(0, DL, MVT::i64), in getAArch64XALUOOp()
2104 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32); in getAArch64XALUOOp()
2116 return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first; in LowerF128Call()
2145 SDValue TVal = DAG.getConstant(1, dl, MVT::i32); in LowerXOR()
2146 SDValue FVal = DAG.getConstant(0, dl, MVT::i32); in LowerXOR()
2150 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXOR()
2174 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) in LowerXOR()
2215 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in LowerADDC_ADDE_SUBC_SUBE()
2256 SDValue TVal = DAG.getConstant(1, dl, MVT::i32); in LowerXALUO()
2257 SDValue FVal = DAG.getConstant(0, dl, MVT::i32); in LowerXALUO()
2262 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXALUO()
2263 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal, in LowerXALUO()
2266 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); in LowerXALUO()
2297 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
2298 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1)); in LowerPREFETCH()
2303 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering"); in LowerFP_EXTEND()
2313 if (Op.getOperand(0).getValueType() != MVT::f128) { in LowerFP_ROUND()
2338 if (InVT.getVectorElementType() == MVT::f16) { in LowerVectorFP_TO_INT()
2339 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT()
2356 MVT ExtVT = in LowerVectorFP_TO_INT()
2357 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()), in LowerVectorFP_TO_INT()
2373 if (Op.getOperand(0).getValueType() == MVT::f16 && in LowerFP_TO_INT()
2378 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
2381 if (Op.getOperand(0).getValueType() != MVT::f128) { in LowerFP_TO_INT()
2406 MVT CastVT = in LowerVectorINT_TO_FP()
2407 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()), in LowerVectorINT_TO_FP()
2430 if (Op.getValueType() == MVT::f16 && in LowerINT_TO_FP()
2434 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2435 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)), in LowerINT_TO_FP()
2440 if (Op.getOperand(0).getValueType() == MVT::i128) in LowerINT_TO_FP()
2445 if (Op.getValueType() != MVT::f128) in LowerINT_TO_FP()
2475 RTLIB::Libcall LC = ArgVT == MVT::f64 ? RTLIB::SINCOS_STRET_F64 in LowerFSINCOS()
2492 if (Op.getValueType() != MVT::f16) in LowerBITCAST()
2495 assert(Op.getOperand(0).getValueType() == MVT::i16); in LowerBITCAST()
2498 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); in LowerBITCAST()
2499 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op); in LowerBITCAST()
2501 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op, in LowerBITCAST()
2502 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)), in LowerBITCAST()
2512 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
2515 case MVT::v2i8: in getExtensionTo64Bits()
2516 case MVT::v2i16: in getExtensionTo64Bits()
2517 return MVT::v2i32; in getExtensionTo64Bits()
2518 case MVT::v4i8: in getExtensionTo64Bits()
2519 return MVT::v4i16; in getExtensionTo64Bits()
2578 MVT TruncVT = MVT::getIntegerVT(EltSize); in skipExtensionForVectorMULL()
2585 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); in skipExtensionForVectorMULL()
2587 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops); in skipExtensionForVectorMULL()
2630 SDValue FPCR_64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i64, in LowerFLT_ROUNDS_()
2632 MVT::i64)); in LowerFLT_ROUNDS_()
2633 SDValue FPCR_32 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, FPCR_64); in LowerFLT_ROUNDS_()
2634 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPCR_32, in LowerFLT_ROUNDS_()
2635 DAG.getConstant(1U << 22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
2636 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, in LowerFLT_ROUNDS_()
2637 DAG.getConstant(22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
2638 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, in LowerFLT_ROUNDS_()
2639 DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
2678 if (VT == MVT::v2i64) in LowerMUL()
2723 if (Ty == MVT::i64) { in LowerINTRINSIC_WO_CHAIN()
2724 SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
2726 Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result); in LowerINTRINSIC_WO_CHAIN()
2727 return DAG.getNode(ISD::BITCAST, dl, MVT::i64, Result); in LowerINTRINSIC_WO_CHAIN()
2782 assert(MemVT == MVT::v4i8 && VT == MVT::v4i16); in LowerTruncateVectorStore()
2793 SDValue Undef = DAG.getUNDEF(MVT::i16); in LowerTruncateVectorStore()
2794 SDValue UndefVec = DAG.getBuildVector(MVT::v4i16, DL, in LowerTruncateVectorStore()
2797 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
2799 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt); in LowerTruncateVectorStore()
2801 Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc); in LowerTruncateVectorStore()
2802 SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerTruncateVectorStore()
2803 Trunc, DAG.getConstant(0, DL, MVT::i64)); in LowerTruncateVectorStore()
3034 MVT ValVT = Ins[i].VT; in LowerFormalArguments()
3042 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other; in LowerFormalArguments()
3044 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) in LowerFormalArguments()
3045 ValVT = MVT::i8; in LowerFormalArguments()
3046 else if (ActualMVT == MVT::i16) in LowerFormalArguments()
3047 ValVT = MVT::i16; in LowerFormalArguments()
3084 if (RegVT == MVT::i32) in LowerFormalArguments()
3086 else if (RegVT == MVT::i64) in LowerFormalArguments()
3088 else if (RegVT == MVT::f16) in LowerFormalArguments()
3090 else if (RegVT == MVT::f32) in LowerFormalArguments()
3092 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
3094 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
3143 MVT MemVT = VA.getValVT(); in LowerFormalArguments()
3190 SmallVector<MVT, 2> RegParmTypes; in LowerFormalArguments()
3191 RegParmTypes.push_back(MVT::i64); in LowerFormalArguments()
3192 RegParmTypes.push_back(MVT::f128); in LowerFormalArguments()
3260 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in saveVarArgRegisters()
3292 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128); in saveVarArgRegisters()
3307 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in saveVarArgRegisters()
3334 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 && in LowerCallResult()
3515 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
3574 MVT ArgVT = Outs[i].VT; in LowerCall()
3591 MVT ValVT = Outs[i].VT; in LowerCall()
3596 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT; in LowerCall()
3599 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) in LowerCall()
3600 ValVT = MVT::i8; in LowerCall()
3601 else if (ActualMVT == MVT::i16) in LowerCall()
3602 ValVT = MVT::i16; in LowerCall()
3687 if (Outs[realArgIdx].ArgVT == MVT::i1) { in LowerCall()
3689 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); in LowerCall()
3690 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg); in LowerCall()
3704 Outs[0].VT == MVT::i64) { in LowerCall()
3705 assert(VA.getLocVT() == MVT::i64 && in LowerCall()
3707 assert(!Ins.empty() && Ins[0].VT == MVT::i64 && in LowerCall()
3756 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64); in LowerCall()
3768 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 || in LowerCall()
3769 VA.getValVT() == MVT::i16) in LowerCall()
3779 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
3837 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()
3871 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
3938 if (Outs[i].ArgVT == MVT::i1) { in LowerReturn()
3942 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); in LowerReturn()
3961 RetOps.push_back(DAG.getRegister(*I, MVT::i64)); in LowerReturn()
3963 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64))); in LowerReturn()
3975 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn()
4130 MVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerDarwinGlobalTLSAddress()
4141 MVT::i64, DL, Chain, DescAddr, in LowerDarwinGlobalTLSAddress()
4164 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), in LowerDarwinGlobalTLSAddress()
4165 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64), in LowerDarwinGlobalTLSAddress()
4194 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerELFTLSDescCallSeq()
4242 DAG.getTargetConstant(0, DL, MVT::i32)), in LowerELFGlobalTLSAddress()
4247 DAG.getTargetConstant(0, DL, MVT::i32)), in LowerELFGlobalTLSAddress()
4277 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12); in LowerELFGlobalTLSAddress()
4279 GV, DL, MVT::i64, 0, in LowerELFGlobalTLSAddress()
4283 DAG.getTargetConstant(0, DL, MVT::i32)), in LowerELFGlobalTLSAddress()
4286 DAG.getTargetConstant(0, DL, MVT::i32)), in LowerELFGlobalTLSAddress()
4312 SDValue TEB = DAG.getRegister(AArch64::X18, MVT::i64); in LowerWindowsGlobalTLSAddress()
4332 TLSIndex = DAG.getLoad(MVT::i32, DL, Chain, TLSIndex, MachinePointerInfo()); in LowerWindowsGlobalTLSAddress()
4356 DAG.getTargetConstant(0, DL, MVT::i32)), in LowerWindowsGlobalTLSAddress()
4396 if (LHS.getValueType() == MVT::f128) { in LowerBR_CC()
4397 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); in LowerBR_CC()
4422 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32); in LowerBR_CC()
4424 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
4430 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); in LowerBR_CC()
4446 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test, in LowerBR_CC()
4447 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
4451 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); in LowerBR_CC()
4462 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test, in LowerBR_CC()
4463 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
4467 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest); in LowerBR_CC()
4473 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS, in LowerBR_CC()
4474 DAG.getConstant(Mask, dl, MVT::i64), Dest); in LowerBR_CC()
4483 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS, in LowerBR_CC()
4484 DAG.getConstant(Mask, dl, MVT::i64), Dest); in LowerBR_CC()
4489 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
4493 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || in LowerBR_CC()
4494 LHS.getValueType() == MVT::f64); in LowerBR_CC()
4501 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32); in LowerBR_CC()
4503 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); in LowerBR_CC()
4505 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerBR_CC()
4506 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, in LowerBR_CC()
4543 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) { in LowerFCOPYSIGN()
4544 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32); in LowerFCOPYSIGN()
4547 } else if (VT == MVT::f64 || VT == MVT::v2f64) { in LowerFCOPYSIGN()
4548 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
4556 } else if (VT == MVT::f16 || VT == MVT::v4f16 || VT == MVT::v8f16) { in LowerFCOPYSIGN()
4557 VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16); in LowerFCOPYSIGN()
4568 if (VT == MVT::f64 || VT == MVT::v2f64) { in LowerFCOPYSIGN()
4569 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec); in LowerFCOPYSIGN()
4570 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec); in LowerFCOPYSIGN()
4571 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec); in LowerFCOPYSIGN()
4577 if (VT == MVT::f16) in LowerFCOPYSIGN()
4579 if (VT == MVT::f32) in LowerFCOPYSIGN()
4581 else if (VT == MVT::f64) in LowerFCOPYSIGN()
4607 if (VT == MVT::i32 || VT == MVT::i64) { in LowerCTPOP()
4608 if (VT == MVT::i32) in LowerCTPOP()
4609 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in LowerCTPOP()
4610 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val); in LowerCTPOP()
4612 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val); in LowerCTPOP()
4614 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, in LowerCTPOP()
4615 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop); in LowerCTPOP()
4617 if (VT == MVT::i64) in LowerCTPOP()
4618 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV); in LowerCTPOP()
4622 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
4623 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && in LowerCTPOP()
4626 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
4636 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP()
4639 DAG.getConstant(Intrinsic::aarch64_neon_uaddlp, DL, MVT::i32), Val); in LowerCTPOP()
4662 if (LHS.getValueType() == MVT::f128) { in LowerSETCC()
4663 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); in LowerSETCC()
4685 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || in LowerSETCC()
4686 LHS.getValueType() == MVT::f64); in LowerSETCC()
4696 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32); in LowerSETCC()
4709 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32); in LowerSETCC()
4713 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerSETCC()
4724 if (LHS.getValueType() == MVT::f128) { in LowerSELECT_CC()
4725 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); in LowerSELECT_CC()
4736 if (LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) { in LowerSELECT_CC()
4737 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in LowerSELECT_CC()
4738 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in LowerSELECT_CC()
4744 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); in LowerSELECT_CC()
4789 } else if (TVal.getValueType() == MVT::i32) { in LowerSELECT_CC()
4862 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || in LowerSELECT_CC()
4863 LHS.getValueType() == MVT::f64); in LowerSELECT_CC()
4892 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32); in LowerSELECT_CC()
4898 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32); in LowerSELECT_CC()
4934 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32); in LowerSELECT()
4980 DAG.getMachineNode(AArch64::JumpTableDest32, DL, MVT::i64, MVT::i64, JT, in LowerBR_JT()
4981 Entry, DAG.getTargetJumpTable(JTI, MVT::i32)); in LowerBR_JT()
4982 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Op.getOperand(0), in LowerBR_JT()
5099 Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32), GROffsAddr, in LowerAAPCS_VASTART()
5106 Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32), VROffsAddr, in LowerAAPCS_VASTART()
5109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in LowerAAPCS_VASTART()
5136 DAG.getConstant(VaListSize, DL, MVT::i32), in LowerVACOPY()
5174 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { in LowerVAARG()
5190 DAG.getLoad(MVT::f64, DL, APStore, VAList, MachinePointerInfo()); in LowerVAARG()
5329 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, in LowerShiftRightParts()
5330 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt); in LowerShiftRightParts()
5335 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64), in LowerShiftRightParts()
5337 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32); in LowerShiftRightParts()
5339 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64), in LowerShiftRightParts()
5342 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, in LowerShiftRightParts()
5343 DAG.getConstant(VTBits, dl, MVT::i64)); in LowerShiftRightParts()
5349 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE, in LowerShiftRightParts()
5351 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32); in LowerShiftRightParts()
5362 DAG.getConstant(VTBits - 1, dl, MVT::i64)) in LowerShiftRightParts()
5384 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, in LowerShiftLeftParts()
5385 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt); in LowerShiftLeftParts()
5390 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64), in LowerShiftLeftParts()
5392 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32); in LowerShiftLeftParts()
5394 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64), in LowerShiftLeftParts()
5397 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, in LowerShiftLeftParts()
5398 DAG.getConstant(VTBits, dl, MVT::i64)); in LowerShiftLeftParts()
5405 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE, in LowerShiftLeftParts()
5407 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32); in LowerShiftLeftParts()
5432 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 || in isFPImmLegal()
5433 (VT == MVT::f16 && Subtarget->hasFullFP16()))) { in isFPImmLegal()
5442 if (VT == MVT::f64) in isFPImmLegal()
5444 else if (VT == MVT::f32) in isFPImmLegal()
5446 else if (VT == MVT::f16 && Subtarget->hasFullFP16()) in isFPImmLegal()
5469 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 || in getEstimate()
5470 VT == MVT::f32 || VT == MVT::v1f32 || in getEstimate()
5471 VT == MVT::v2f32 || VT == MVT::v4f32)) { in getEstimate()
5478 ExtraSteps = VT.getScalarType() == MVT::f64 ? 3 : 2; in getEstimate()
5660 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
5708 if (VT != MVT::Other && VT.getSizeInBits() == 64) { in getRegForInlineAsmConstraint()
5750 if (Op.getValueType() == MVT::i64) in LowerAsmOperandForConstraint()
5751 Result = DAG.getRegister(AArch64::XZR, MVT::i64); in LowerAsmOperandForConstraint()
5753 Result = DAG.getRegister(AArch64::WZR, MVT::i32); in LowerAsmOperandForConstraint()
5869 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64); in LowerAsmOperandForConstraint()
5890 MVT EltTy = VT.getVectorElementType().getSimpleVT(); in WidenVector()
5891 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize); in WidenVector()
5895 V64Reg, DAG.getConstant(0, DL, MVT::i32)); in WidenVector()
5910 MVT EltTy = VT.getVectorElementType().getSimpleVT(); in NarrowVector()
5911 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2); in NarrowVector()
6036 DAG.getConstant(NumSrcElts, dl, MVT::i64)); in ReconstructShuffle()
6042 DAG.getConstant(0, dl, MVT::i64)); in ReconstructShuffle()
6047 DAG.getConstant(0, dl, MVT::i64)); in ReconstructShuffle()
6050 DAG.getConstant(NumSrcElts, dl, MVT::i64)); in ReconstructShuffle()
6055 DAG.getConstant(Imm, dl, MVT::i32)); in ReconstructShuffle()
6395 DAG.getConstant(0, DL, MVT::i64)); in tryFormConcatFromShuffle()
6399 DAG.getConstant(0, DL, MVT::i64)); in tryFormConcatFromShuffle()
6448 if (VT.getVectorElementType() == MVT::i32 || in GeneratePerfectShuffle()
6449 VT.getVectorElementType() == MVT::f32) in GeneratePerfectShuffle()
6452 if (VT.getVectorElementType() == MVT::i16 || in GeneratePerfectShuffle()
6453 VT.getVectorElementType() == MVT::f16) in GeneratePerfectShuffle()
6456 assert(VT.getVectorElementType() == MVT::i8); in GeneratePerfectShuffle()
6464 if (EltTy == MVT::i8) in GeneratePerfectShuffle()
6466 else if (EltTy == MVT::i16 || EltTy == MVT::f16) in GeneratePerfectShuffle()
6468 else if (EltTy == MVT::i32 || EltTy == MVT::f32) in GeneratePerfectShuffle()
6470 else if (EltTy == MVT::i64 || EltTy == MVT::f64) in GeneratePerfectShuffle()
6477 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); in GeneratePerfectShuffle()
6485 DAG.getConstant(Imm, dl, MVT::i32)); in GeneratePerfectShuffle()
6522 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32)); in GenerateTBL()
6526 MVT IndexVT = MVT::v8i8; in GenerateTBL()
6529 IndexVT = MVT::v16i8; in GenerateTBL()
6539 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
6542 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst, in GenerateTBL()
6547 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
6550 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst, in GenerateTBL()
6562 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32), V1Cst, in GenerateTBL()
6571 if (EltType == MVT::i8) in getDUPLANEOp()
6573 if (EltType == MVT::i16 || EltType == MVT::f16) in getDUPLANEOp()
6575 if (EltType == MVT::i32 || EltType == MVT::f32) in getDUPLANEOp()
6577 if (EltType == MVT::i64 || EltType == MVT::f64) in getDUPLANEOp()
6630 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64)); in LowerVECTOR_SHUFFLE()
6647 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
6651 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
6689 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64); in LowerVECTOR_SHUFFLE()
6697 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64); in LowerVECTOR_SHUFFLE()
6702 ScalarVT = MVT::i32; in LowerVECTOR_SHUFFLE()
6763 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v2i64 : MVT::f64; in tryAdvSIMDModImm64()
6770 DAG.getConstant(Value, dl, MVT::i32)); in tryAdvSIMDModImm64()
6785 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; in tryAdvSIMDModImm32()
6812 DAG.getConstant(Value, dl, MVT::i32), in tryAdvSIMDModImm32()
6813 DAG.getConstant(Shift, dl, MVT::i32)); in tryAdvSIMDModImm32()
6816 DAG.getConstant(Value, dl, MVT::i32), in tryAdvSIMDModImm32()
6817 DAG.getConstant(Shift, dl, MVT::i32)); in tryAdvSIMDModImm32()
6833 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; in tryAdvSIMDModImm16()
6852 DAG.getConstant(Value, dl, MVT::i32), in tryAdvSIMDModImm16()
6853 DAG.getConstant(Shift, dl, MVT::i32)); in tryAdvSIMDModImm16()
6856 DAG.getConstant(Value, dl, MVT::i32), in tryAdvSIMDModImm16()
6857 DAG.getConstant(Shift, dl, MVT::i32)); in tryAdvSIMDModImm16()
6872 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; in tryAdvSIMDModImm321s()
6888 DAG.getConstant(Value, dl, MVT::i32), in tryAdvSIMDModImm321s()
6889 DAG.getConstant(Shift, dl, MVT::i32)); in tryAdvSIMDModImm321s()
6903 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8; in tryAdvSIMDModImm8()
6910 DAG.getConstant(Value, dl, MVT::i32)); in tryAdvSIMDModImm8()
6925 MVT MovTy; in tryAdvSIMDModImmFP()
6930 MovTy = isWide ? MVT::v4f32 : MVT::v2f32; in tryAdvSIMDModImmFP()
6935 MovTy = MVT::v2f64; in tryAdvSIMDModImmFP()
6941 DAG.getConstant(Value, dl, MVT::i32)); in tryAdvSIMDModImmFP()
7076 DAG.getConstant(Intrin, DL, MVT::i32), X, Y, in tryLowerToSLI()
7152 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32); in NormalizeBuildVector()
7154 Lane = DAG.getUNDEF(MVT::i32); in NormalizeBuildVector()
7156 assert(Lane.getValueType() == MVT::i32 && in NormalizeBuildVector()
7339 DAG.getConstant(0, dl, MVT::i64)); in LowerBUILD_VECTOR()
7342 DAG.getConstant(NumElts, dl, MVT::i64)); in LowerBUILD_VECTOR()
7382 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) && in LowerBUILD_VECTOR()
7387 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits()); in LowerBUILD_VECTOR()
7417 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR()
7476 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR()
7500 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in LowerINSERT_VECTOR_ELT()
7501 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 || in LowerINSERT_VECTOR_ELT()
7502 VT == MVT::v8f16) in LowerINSERT_VECTOR_ELT()
7505 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerINSERT_VECTOR_ELT()
7506 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) in LowerINSERT_VECTOR_ELT()
7534 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in LowerEXTRACT_VECTOR_ELT()
7535 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 || in LowerEXTRACT_VECTOR_ELT()
7536 VT == MVT::v8f16) in LowerEXTRACT_VECTOR_ELT()
7539 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerEXTRACT_VECTOR_ELT()
7540 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) in LowerEXTRACT_VECTOR_ELT()
7550 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8) in LowerEXTRACT_VECTOR_ELT()
7551 ExtrTy = MVT::i32; in LowerEXTRACT_VECTOR_ELT()
7682 DAG.getConstant(Cnt, DL, MVT::i32)); in LowerVectorSRA_SRL_SHL()
7685 MVT::i32), in LowerVectorSRA_SRL_SHL()
7694 DAG.getConstant(Cnt, DL, MVT::i32)); in LowerVectorSRA_SRL_SHL()
7706 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0), in LowerVectorSRA_SRL_SHL()
7830 if (LHS.getValueType().getVectorElementType() == MVT::f16) { in LowerVSETCC()
7832 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS); in LowerVSETCC()
7833 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS); in LowerVSETCC()
7834 SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC); in LowerVSETCC()
7836 CmpVT = MVT::v4i32; in LowerVSETCC()
7841 assert(LHS.getValueType().getVectorElementType() == MVT::f32 || in LowerVSETCC()
7842 LHS.getValueType().getVectorElementType() == MVT::f64); in LowerVSETCC()
7878 DAG.getConstant(0, DL, MVT::i64)); in getReductionSDNode()
7899 DAG.getConstant(Intrinsic::aarch64_neon_fmaxnmv, dl, MVT::i32), in LowerVECREDUCE()
7906 DAG.getConstant(Intrinsic::aarch64_neon_fminnmv, dl, MVT::i32), in LowerVECREDUCE()
7922 MVT VT = Op.getSimpleValueType(); in LowerATOMIC_LOAD_SUB()
7939 MVT VT = Op.getSimpleValueType(); in LowerATOMIC_LOAD_AND()
7959 Size = DAG.getNode(ISD::SRL, dl, MVT::i64, Size, in LowerWindowsDYNAMIC_STACKALLOC()
7960 DAG.getConstant(4, dl, MVT::i64)); in LowerWindowsDYNAMIC_STACKALLOC()
7963 DAG.getNode(AArch64ISD::CALL, dl, DAG.getVTList(MVT::Other, MVT::Glue), in LowerWindowsDYNAMIC_STACKALLOC()
7964 Chain, Callee, DAG.getRegister(AArch64::X15, MVT::i64), in LowerWindowsDYNAMIC_STACKALLOC()
7971 Size = DAG.getNode(ISD::SHL, dl, MVT::i64, Size, in LowerWindowsDYNAMIC_STACKALLOC()
7972 DAG.getConstant(4, dl, MVT::i64)); in LowerWindowsDYNAMIC_STACKALLOC()
7991 SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64); in LowerDYNAMIC_STACKALLOC()
7993 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size); in LowerDYNAMIC_STACKALLOC()
8006 SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64); in LowerDYNAMIC_STACKALLOC()
8008 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size); in LowerDYNAMIC_STACKALLOC()
8045 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
8071 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
8083 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
8094 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
8104 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
8113 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
8606 AlignmentIsAcceptable(MVT::v2i64, 16)) in getOptimalMemOpType()
8607 return MVT::v2i64; in getOptimalMemOpType()
8608 if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, 16)) in getOptimalMemOpType()
8609 return MVT::f128; in getOptimalMemOpType()
8610 if (Size >= 8 && AlignmentIsAcceptable(MVT::i64, 8)) in getOptimalMemOpType()
8611 return MVT::i64; in getOptimalMemOpType()
8612 if (Size >= 4 && AlignmentIsAcceptable(MVT::i32, 4)) in getOptimalMemOpType()
8613 return MVT::i32; in getOptimalMemOpType()
8614 return MVT::Other; in getOptimalMemOpType()
8719 case MVT::f32: in isFMAFasterThanFMulAndFAdd()
8720 case MVT::f64: in isFMAFasterThanFMulAndFAdd()
8747 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && in isDesirableToCommuteWithShift()
8835 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), in performIntegerAbsCombine()
8838 DAG.getConstant(AArch64CC::PL, DL, MVT::i32), in performIntegerAbsCombine()
8866 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
8888 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
8982 DAG.getConstant(ShiftAmt, DL, MVT::i64)); in performMulCombine()
8995 DAG.getConstant(TrailingZeroes, DL, MVT::i64)); in performMulCombine()
9053 if (VT != MVT::f32 && VT != MVT::f64) in performIntToFpCombine()
9101 MVT FloatTy = Op.getSimpleValueType().getVectorElementType(); in performFpToIntCombine()
9106 MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); in performFpToIntCombine()
9122 MVT ResTy; in performFpToIntCombine()
9128 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64; in performFpToIntCombine()
9131 ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64; in performFpToIntCombine()
9135 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFpToIntCombine()
9138 assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) && in performFpToIntCombine()
9147 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), in performFpToIntCombine()
9148 Op->getOperand(0), DAG.getConstant(C, DL, MVT::i32)); in performFpToIntCombine()
9175 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); in performFDivCombine()
9180 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType(); in performFDivCombine()
9195 MVT ResTy; in performFDivCombine()
9201 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64; in performFDivCombine()
9204 ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64; in performFDivCombine()
9208 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFDivCombine()
9221 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), ConvInput, in performFDivCombine()
9222 DAG.getConstant(C, DL, MVT::i32)); in performFDivCombine()
9257 if (VT != MVT::i32 && VT != MVT::i64) in tryCombineToEXTR()
9286 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
9358 if (VT != MVT::i32 && VT != MVT::i64) in performSRLCombine()
9371 if (VT == MVT::i32 && ShiftAmt == 16 && in performSRLCombine()
9374 if (VT == MVT::i64 && ShiftAmt == 32 && in performSRLCombine()
9440 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64); in performBitcastCombine()
9443 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32); in performBitcastCombine()
9476 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) && in performConcatVectorsCombine()
9478 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine()
9501 DAG.getConstant(0, dl, MVT::i64)); in performConcatVectorsCombine()
9516 MVT RHSTy = RHS.getValueType().getSimpleVT(); in performConcatVectorsCombine()
9524 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(), in performConcatVectorsCombine()
9565 if (Vec.getValueType() == MVT::v4i32) in tryCombineFixedPointConvert()
9566 VecResTy = MVT::v4f32; in tryCombineFixedPointConvert()
9567 else if (Vec.getValueType() == MVT::v2i64) in tryCombineFixedPointConvert()
9568 VecResTy = MVT::v2f64; in tryCombineFixedPointConvert()
9615 MVT NarrowTy = N.getSimpleValueType(); in tryExtendDUPToExtractHigh()
9619 MVT ElementTy = NarrowTy.getVectorElementType(); in tryExtendDUPToExtractHigh()
9621 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); in tryExtendDUPToExtractHigh()
9626 DAG.getConstant(NumElems, dl, MVT::i64)); in tryExtendDUPToExtractHigh()
9743 if (CmpVT != MVT::i32 && CmpVT != MVT::i64) in performSetccAddFolding()
9752 MVT::i32); in performSetccAddFolding()
9782 MVT VT = N->getSimpleValueType(0); in performAddSubLongCombine()
9855 MVT ElemTy = N->getSimpleValueType(0).getScalarType(); in tryCombineShiftImm()
9904 DAG.getConstant(-ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
9908 DAG.getConstant(ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
9926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32, in tryCombineCRC32()
9937 DAG.getConstant(0, dl, MVT::i64)); in combineAcrossLanesIntrinsic()
10067 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount); in performExtendCombine()
10083 DAG.getConstant(0, DL, MVT::i64)); in performExtendCombine()
10085 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64)); in performExtendCombine()
10124 DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, in splitStoreSplat()
10125 DAG.getConstant(BaseOffset + Offset, DL, MVT::i64)); in splitStoreSplat()
10197 ZeroVT = MVT::i32; in replaceZeroVectorStore()
10200 ZeroVT = MVT::i64; in replaceZeroVectorStore()
10297 if (VT.getVectorNumElements() < 2 || VT == MVT::v2i64) in splitStores()
10321 DAG.getConstant(0, DL, MVT::i64)); in splitStores()
10323 DAG.getConstant(NumElts, DL, MVT::i64)); in splitStores()
10328 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, in splitStores()
10329 DAG.getConstant(8, DL, MVT::i64)); in splitStores()
10394 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); in performPostLD1Combine()
10418 EVT Tys[3] = { VT, MVT::i64, MVT::Other }; in performPostLD1Combine()
10569 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); in performNEONPostLDSTCombine()
10586 Tys[n++] = MVT::i64; // Type of write back register in performNEONPostLDSTCombine()
10587 Tys[n] = MVT::Other; // Type of the chain in performNEONPostLDSTCombine()
10619 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8) in checkValueWidth()
10620 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) { in checkValueWidth()
10628 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
10629 || (TypeNode->getVT() == MVT::i16 && width == 16)) { in checkValueWidth()
10637 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
10638 || (TypeNode->getVT() == MVT::i16 && width == 16)) { in checkValueWidth()
10901 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) in performBRCONDCombine()
10917 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); in performBRCONDCombine()
10919 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); in performBRCONDCombine()
11020 return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc, in performTBZCombine()
11021 DAG.getConstant(Bit, DL, MVT::i64), N->getOperand(3)); in performTBZCombine()
11034 CCVT.getVectorElementType() != MVT::i1) in performVSelectCombine()
11070 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) && in performSelectCombine()
11080 if (SrcVT == MVT::i1) in performSelectCombine()
11174 SDValue Result = DAG.getGlobalAddress(GV, DL, MVT::i64, Offset); in performGlobalAddressCombine()
11175 return DAG.getNode(ISD::SUB, DL, MVT::i64, Result, in performGlobalAddressCombine()
11176 DAG.getConstant(MinOffset, DL, MVT::i64)); in performGlobalAddressCombine()
11290 MVT::Glue) in isUsedByReturnOnly()
11394 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16) in ReplaceBITCASTResults()
11398 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32, in ReplaceBITCASTResults()
11399 DAG.getUNDEF(MVT::i32), Op, in ReplaceBITCASTResults()
11400 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)), in ReplaceBITCASTResults()
11402 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op); in ReplaceBITCASTResults()
11403 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op)); in ReplaceBITCASTResults()
11422 SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N); in splitInt128()
11423 SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, in splitInt128()
11424 DAG.getNode(ISD::SRL, DL, MVT::i128, N, in splitInt128()
11425 DAG.getConstant(64, DL, MVT::i64))); in splitInt128()
11432 SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i64); in createGPRPairNode()
11434 DAG.getNode(ISD::SRL, dl, MVT::i128, V, DAG.getConstant(64, dl, MVT::i64)), in createGPRPairNode()
11435 dl, MVT::i64); in createGPRPairNode()
11439 DAG.getTargetConstant(AArch64::XSeqPairsClassRegClassID, dl, MVT::i32); in createGPRPairNode()
11440 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); in createGPRPairNode()
11441 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode()
11444 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); in createGPRPairNode()
11451 assert(N->getValueType(0) == MVT::i128 && in ReplaceCMP_SWAP_128Results()
11486 Opcode, SDLoc(N), DAG.getVTList(MVT::Untyped, MVT::Other), Ops); in ReplaceCMP_SWAP_128Results()
11492 Results.push_back(DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
11494 Results.push_back(DAG.getTargetExtractSubreg(SubReg2, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
11506 DAG.getVTList(MVT::i64, MVT::i64, MVT::i32, MVT::Other), Ops); in ReplaceCMP_SWAP_128Results()
11552 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion"); in ReplaceNodeResults()
11574 AArch64TargetLowering::getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
11577 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 || in getPreferredVectorAction()
11578 VT == MVT::v1f32) in getPreferredVectorAction()