996   case AArch64ISD::CSEL: {  in computeKnownBitsForTargetNode()
1096   case AArch64ISD::CSEL:              return "AArch64ISD::CSEL";  in getTargetNodeName()
2151     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,  in LowerXOR()
2201     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,  in LowerXOR()
2263   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,  in LowerXALUO()
4681     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
4701     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);  in LowerSETCC()
4711         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSETCC()
4714     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSETCC()
4746     unsigned Opcode = AArch64ISD::CSEL;  in LowerSELECT_CC()
4821       if (Opcode != AArch64ISD::CSEL) {  in LowerSELECT_CC()
4834     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&  in LowerSELECT_CC()
4893   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSELECT_CC()
4899     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSELECT_CC()
4936     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,  in LowerSELECT()
5339       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),  in LowerShiftRightParts()
5353   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,  in LowerShiftRightParts()
5364   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,  in LowerShiftRightParts()
5394       DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),  in LowerShiftLeftParts()
5408   SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,  in LowerShiftLeftParts()
5415   SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,  in LowerShiftLeftParts()
8837         return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,  in performIntegerAbsCombine()
8880   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
9683   if (Op.getOpcode() != AArch64ISD::CSEL)  in isSetCC()
9762   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
11230   case AArch64ISD::CSEL:  in PerformDAGCombine()