2150     SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);  in LowerXOR()  local
2152                        CCVal, Overflow);  in LowerXOR()
2194     SDValue CCVal;  in LowerXOR()  local
2195     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerXOR()
2202                        CCVal, Cmp);  in LowerXOR()
2262   SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);  in LowerXALUO()  local
2264                          CCVal, Overflow);  in LowerXALUO()
4422     SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);  in LowerBR_CC()  local
4424     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
4487     SDValue CCVal;  in LowerBR_CC()  local
4488     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerBR_CC()
4489     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
4674     SDValue CCVal;  in LowerSETCC()  local
4676         getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);  in LowerSETCC()
4681     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
4855     SDValue CCVal;  in LowerSELECT_CC()  local
4856     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerSELECT_CC()
4858     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);  in LowerSELECT_CC()
4919   SDValue CCVal = Op->getOperand(0);  in LowerSELECT()  local
4926   if (isOverflowIntrOpRes(CCVal)) {  in LowerSELECT()
4928     if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))  in LowerSELECT()
4933     std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);  in LowerSELECT()
4934     SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);  in LowerSELECT()  local
4937                        CCVal, Overflow);  in LowerSELECT()
4943   if (CCVal.getOpcode() == ISD::SETCC) {  in LowerSELECT()
4944     LHS = CCVal.getOperand(0);  in LowerSELECT()
4945     RHS = CCVal.getOperand(1);  in LowerSELECT()
4946     CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();  in LowerSELECT()
4948     LHS = CCVal;  in LowerSELECT()
4949     RHS = DAG.getConstant(0, DL, CCVal.getValueType());  in LowerSELECT()
5337   SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);  in LowerShiftRightParts()  local
5340                   HiBitsForLo, CCVal, Cmp);  in LowerShiftRightParts()
5351   CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);  in LowerShiftRightParts()
5354                            LoForNormalShift, CCVal, Cmp);  in LowerShiftRightParts()
5365                            HiForNormalShift, CCVal, Cmp);  in LowerShiftRightParts()
5392   SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);  in LowerShiftLeftParts()  local
5395                   LoBitsForHi, CCVal, Cmp);  in LowerShiftLeftParts()
5407   CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);  in LowerShiftLeftParts()
5409                            HiForNormalShift, CCVal, Cmp);  in LowerShiftLeftParts()
5416                            LoForNormalShift, CCVal, Cmp);  in LowerShiftLeftParts()
8877   SDValue CCVal;  in BuildSDIVPow2()  local
8878   SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);  in BuildSDIVPow2()
8880   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
9746   SDValue CCVal;  in performSetccAddFolding()  local
9750     CCVal = DAG.getConstant(  in performSetccAddFolding()
9758                       CCVal, DAG, dl);  in performSetccAddFolding()
9762   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
10879   SDValue CCVal = N->getOperand(2);  in performBRCONDCombine()  local
10882   assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");  in performBRCONDCombine()
10883   unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();  in performBRCONDCombine()