Lines Matching refs:getOffsetReg
124 unsigned getOffsetReg() const { in getOffsetReg() function in __anone69598a70111::AArch64FastISel::Address
685 if (Addr.getOffsetReg()) in computeAddress()
760 if (Addr.getOffsetReg()) in computeAddress()
821 if (Addr.getOffsetReg()) in computeAddress()
853 if (!Addr.getReg() || Addr.getOffsetReg()) in computeAddress()
890 if (!Addr.getOffsetReg()) { in computeAddress()
1011 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg()) in simplifyAddress()
1015 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg()) in simplifyAddress()
1021 if ((ImmediateOffsetNeedsLowering || Addr.getOffsetReg()) && Addr.isFIBase()) in simplifyAddress()
1039 /*TODO:IsKill=*/false, Addr.getOffsetReg(), in simplifyAddress()
1044 /*TODO:IsKill=*/false, Addr.getOffsetReg(), in simplifyAddress()
1049 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1053 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1057 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1110 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1111 if (Addr.getOffsetReg()) { in addLoadStoreOperands()
1116 MIB.addReg(Addr.getOffsetReg()); in addLoadStoreOperands()
1822 Addr.getOffsetReg(); in emitLoad()
2113 Addr.getOffsetReg(); in emitStore()