197   bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
234   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
265   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
269   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
273   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1150   MVT SrcVT = RetVT;  in emitAddSub()  local
1177     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1275     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);  in emitAddSub()
2848   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectFPToInt()  local
2849   if (SrcVT == MVT::f128 || SrcVT == MVT::f16)  in selectFPToInt()
2853   if (SrcVT == MVT::f64) {  in selectFPToInt()
2888   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectIntToFP()  local
2891   if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {  in selectIntToFP()
2893         emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);  in selectIntToFP()
2900   if (SrcVT == MVT::i64) {  in selectIntToFP()
3060       MVT SrcVT = ArgVT;  in processCallArgs()  local
3061       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3070       MVT SrcVT = ArgVT;  in processCallArgs()  local
3071       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3901   MVT SrcVT = SrcEVT.getSimpleVT();  in selectTrunc()  local
3904   if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&  in selectTrunc()
3905       SrcVT != MVT::i8)  in selectTrunc()
3922   if (SrcVT == MVT::i64) {  in selectTrunc()
4054 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSL_ri()  argument
4057   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSL_ri()
4059   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSL_ri()
4060           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSL_ri()
4068   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSL_ri()
4074     if (RetVT == SrcVT) {  in emitLSL_ri()
4081       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSL_ri()
4121   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSL_ri()
4161 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSR_ri()  argument
4164   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSR_ri()
4166   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSR_ri()
4167           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSR_ri()
4175   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4181     if (RetVT == SrcVT) {  in emitLSR_ri()
4188       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4226     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4230     SrcVT = RetVT;  in emitLSR_ri()
4231     SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4242   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSR_ri()
4282 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitASR_ri()  argument
4285   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitASR_ri()
4287   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitASR_ri()
4288           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitASR_ri()
4296   unsigned SrcBits = SrcVT.getSizeInBits();  in emitASR_ri()
4302     if (RetVT == SrcVT) {  in emitASR_ri()
4309       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitASR_ri()
4351   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitASR_ri()
4364 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4374       ((SrcVT !=  MVT::i1) && (SrcVT !=  MVT::i8) &&  in emitIntExt()
4375        (SrcVT !=  MVT::i16) && (SrcVT !=  MVT::i32)))  in emitIntExt()
4381   switch (SrcVT.SimpleTy) {  in emitIntExt()
4474                                          MVT SrcVT) {  in optimizeIntExtLoad()  argument
4502   if (RetVT != MVT::i64 || SrcVT > MVT::i32) {  in optimizeIntExtLoad()
4531   MVT SrcVT;  in selectIntExt()  local
4535   if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))  in selectIntExt()
4539   if (optimizeIntExtLoad(I, RetVT, SrcVT))  in selectIntExt()
4551       if (RetVT == MVT::i64 && SrcVT != MVT::i64) {  in selectIntExt()
4573   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()
4645       MVT SrcVT = VT;  in selectMul()  local
4651             SrcVT = VT;  in selectMul()
4660             SrcVT = VT;  in selectMul()
4673           emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);  in selectMul()
4711     MVT SrcVT = RetVT;  in selectShift()  local
4718           SrcVT = TmpVT;  in selectShift()
4727           SrcVT = TmpVT;  in selectShift()
4742       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4745       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4748       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4790   MVT RetVT, SrcVT;  in selectBitCast()  local
4792   if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))  in selectBitCast()
4798   if (RetVT == MVT::f32 && SrcVT == MVT::i32)  in selectBitCast()
4800   else if (RetVT == MVT::f64 && SrcVT == MVT::i64)  in selectBitCast()
4802   else if (RetVT == MVT::i32 && SrcVT == MVT::f32)  in selectBitCast()
4804   else if (RetVT == MVT::i64 && SrcVT == MVT::f64)  in selectBitCast()