Lines Matching refs:RetVT
197 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
202 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
205 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
208 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
211 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
216 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
226 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
227 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
236 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
240 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
243 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
245 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
249 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
251 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
253 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
256 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
257 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
259 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
261 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
263 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
265 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
267 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
269 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
271 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
273 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
285 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
1127 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, in emitAddSub() argument
1132 switch (RetVT.SimpleTy) { in emitAddSub()
1150 MVT SrcVT = RetVT; in emitAddSub()
1151 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1177 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1183 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1186 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1190 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1206 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1214 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1234 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1259 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1277 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1281 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1291 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rr()
1300 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rr()
1319 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1324 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_ri()
1342 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_ri()
1364 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1374 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rs()
1378 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1387 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rs()
1407 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1417 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rx()
1429 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rx()
1474 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, in emitICmp() argument
1476 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false, in emitICmp()
1480 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri() argument
1482 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm, in emitICmp_ri()
1486 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) { in emitFCmp() argument
1487 if (RetVT != MVT::f32 && RetVT != MVT::f64) in emitFCmp()
1503 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1514 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1521 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, in emitAdd() argument
1523 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult, in emitAdd()
1551 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS, in emitSub() argument
1553 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult, in emitSub()
1557 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1560 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rr()
1564 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1569 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rs()
1574 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
1599 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1621 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1637 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1649 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1651 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp()
1652 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp()
1658 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_ri() argument
1671 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1697 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1698 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_ri()
1704 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_rs() argument
1717 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1722 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1740 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp_rs()
1741 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_rs()
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri() argument
1749 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm); in emitAnd_ri()
1752 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1828 bool IsRet64Bit = RetVT == MVT::i64; in emitLoad()
1877 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1975 MVT RetVT = VT; in selectLoad() local
1979 if (isTypeSupported(ZE->getType(), RetVT)) in selectLoad()
1982 RetVT = VT; in selectLoad()
1984 if (isTypeSupported(SE->getType(), RetVT)) in selectLoad()
1987 RetVT = VT; in selectLoad()
1993 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
2016 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
3119 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall() argument
3129 if (RetVT != MVT::isVoid) { in finishCall()
3132 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC)); in finishCall()
3186 MVT RetVT; in fastLowerCall() local
3188 RetVT = MVT::isVoid; in fastLowerCall()
3189 else if (!isTypeLegal(CLI.RetTy, RetVT)) in fastLowerCall()
3279 return finishCall(CLI, RetVT, NumBytes); in fastLowerCall()
3354 MVT RetVT; in foldXALUIntrinsic() local
3358 if (!isTypeLegal(RetTy, RetVT)) in foldXALUIntrinsic()
3361 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldXALUIntrinsic()
3533 MVT RetVT; in fastLowerIntrinsicCall() local
3534 if (!isTypeLegal(II->getType(), RetVT)) in fastLowerIntrinsicCall()
3537 if (RetVT != MVT::f32 && RetVT != MVT::f64) in fastLowerIntrinsicCall()
3546 bool Is64Bit = RetVT == MVT::f64; in fastLowerIntrinsicCall()
3988 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitMul_rr() argument
3991 switch (RetVT.SimpleTy) { in emitMul_rr()
3996 RetVT = MVT::i32; in emitMul_rr()
4003 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
4008 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitSMULL_rr() argument
4010 if (RetVT != MVT::i64) in emitSMULL_rr()
4018 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitUMULL_rr() argument
4020 if (RetVT != MVT::i64) in emitUMULL_rr()
4028 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr() argument
4033 switch (RetVT.SimpleTy) { in emitLSL_rr()
4042 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4054 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
4057 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4062 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSL_ri()
4063 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSL_ri()
4065 bool Is64Bit = (RetVT == MVT::i64); in emitLSL_ri()
4067 unsigned DstBits = RetVT.getSizeInBits(); in emitLSL_ri()
4074 if (RetVT == SrcVT) { in emitLSL_ri()
4081 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4121 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4134 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSR_rr() argument
4139 switch (RetVT.SimpleTy) { in emitLSR_rr()
4148 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4161 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4164 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4169 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSR_ri()
4170 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSR_ri()
4172 bool Is64Bit = (RetVT == MVT::i64); in emitLSR_ri()
4174 unsigned DstBits = RetVT.getSizeInBits(); in emitLSR_ri()
4181 if (RetVT == SrcVT) { in emitLSR_ri()
4188 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4221 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4226 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4230 SrcVT = RetVT; in emitLSR_ri()
4242 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4255 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitASR_rr() argument
4260 switch (RetVT.SimpleTy) { in emitASR_rr()
4269 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4271 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false); in emitASR_rr()
4282 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4285 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4290 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitASR_ri()
4291 RetVT == MVT::i64) && "Unexpected return value type."); in emitASR_ri()
4293 bool Is64Bit = (RetVT == MVT::i64); in emitASR_ri()
4295 unsigned DstBits = RetVT.getSizeInBits(); in emitASR_ri()
4302 if (RetVT == SrcVT) { in emitASR_ri()
4309 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4342 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitASR_ri()
4351 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4473 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, in optimizeIntExtLoad() argument
4502 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4530 MVT RetVT; in selectIntExt() local
4532 if (!isTypeSupported(I->getType(), RetVT)) in selectIntExt()
4539 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4551 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4573 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4701 MVT RetVT; in selectShift() local
4702 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true)) in selectShift()
4705 if (RetVT.isVector()) in selectShift()
4711 MVT SrcVT = RetVT; in selectShift()
4742 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4745 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4748 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4772 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4775 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4778 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4790 MVT RetVT, SrcVT; in selectBitCast() local
4794 if (!isTypeLegal(I->getType(), RetVT)) in selectBitCast()
4798 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4800 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4802 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4804 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()
4810 switch (RetVT.SimpleTy) { in selectBitCast()
4831 MVT RetVT; in selectFRem() local
4832 if (!isTypeLegal(I->getType(), RetVT)) in selectFRem()
4836 switch (RetVT.SimpleTy) { in selectFRem()