239   unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
257   unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
259   unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
261   unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
263   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
265   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
267   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
269   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
271   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
273   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1532 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,  in emitAdd_ri_()  argument
1536     ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);  in emitAdd_ri_()
1538     ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);  in emitAdd_ri_()
1547   ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);  in emitAdd_ri_()
3622     bool Op0IsKill = hasTrivialKill(II->getOperand(0));  in fastLowerIntrinsicCall()  local
3624     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);  in fastLowerIntrinsicCall()
3988 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitMul_rr()  argument
4004   return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,  in emitMul_rr()
4008 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitSMULL_rr()  argument
4014                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitSMULL_rr()
4018 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitUMULL_rr()  argument
4024                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitUMULL_rr()
4028 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSL_rr()  argument
4047   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSL_rr()
4055                                      bool Op0IsKill, uint64_t Shift,  in emitLSL_ri()  argument
4078           .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSL_ri()
4126         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSL_ri()
4129     Op0IsKill = true;  in emitLSL_ri()
4131   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSL_ri()
4134 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSR_rr()  argument
4150     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);  in emitLSR_rr()
4152     Op0IsKill = Op1IsKill = true;  in emitLSR_rr()
4154   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSR_rr()
4162                                      bool Op0IsKill, uint64_t Shift,  in emitLSR_ri()  argument
4185       .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSR_ri()
4229     Op0IsKill = true;  in emitLSR_ri()
4247         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSR_ri()
4250     Op0IsKill = true;  in emitLSR_ri()
4252   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSR_ri()
4255 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitASR_rr()  argument
4273     Op0IsKill = Op1IsKill = true;  in emitASR_rr()
4275   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitASR_rr()
4283                                      bool Op0IsKill, uint64_t Shift,  in emitASR_ri()  argument
4306       .addReg(Op0, getKillRegState(Op0IsKill));  in emitASR_ri()
4356         .addReg(Op0, getKillRegState(Op0IsKill))  in emitASR_ri()
4359     Op0IsKill = true;  in emitASR_ri()
4361   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitASR_ri()
4737     bool Op0IsKill = hasTrivialKill(Op0);  in selectShift()  local
4742       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4745       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4748       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4761   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectShift()  local
4772     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4775     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4778     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4820   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBitCast()  local
4821   unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);  in selectBitCast()