Lines Matching refs:MVT
183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
188 bool simplifyAddress(Address &Addr, MVT VT);
197 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
202 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
205 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
208 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
211 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
216 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
226 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
227 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
228 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
230 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
232 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
234 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
235 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
236 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
239 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
240 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
243 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
245 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
249 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
251 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
253 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
256 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
257 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
259 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
261 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
263 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
265 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
267 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
269 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
271 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
273 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
276 unsigned materializeInt(const ConstantInt *CI, MVT VT);
277 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
283 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
285 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
331 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor()
335 case MVT::i1: // fall-through in getImplicitScaleFactor()
336 case MVT::i8: in getImplicitScaleFactor()
338 case MVT::i16: in getImplicitScaleFactor()
340 case MVT::i32: // fall-through in getImplicitScaleFactor()
341 case MVT::f32: in getImplicitScaleFactor()
343 case MVT::i64: // fall-through in getImplicitScaleFactor()
344 case MVT::f64: in getImplicitScaleFactor()
358 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 && in fastMaterializeAlloca()
381 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt()
382 if (VT > MVT::i64) in materializeInt()
389 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
391 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
398 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP()
404 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
408 bool Is64Bit = (VT == MVT::f64); in materializeFP()
510 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
525 MVT VT; in fastMaterializeFloatZero()
529 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
532 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero()
746 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill, in computeAddress()
844 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill, in computeAddress()
950 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
954 if (evt == MVT::Other || !evt.isSimple()) in isTypeLegal()
959 if (VT == MVT::f128) in isTypeLegal()
971 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported()
980 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
994 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress()
1038 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1043 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1049 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1053 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1057 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1075 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset); in simplifyAddress()
1077 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset); in simplifyAddress()
1127 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, in emitAddSub()
1135 case MVT::i1: in emitAddSub()
1138 case MVT::i8: in emitAddSub()
1142 case MVT::i16: in emitAddSub()
1146 case MVT::i32: // fall-through in emitAddSub()
1147 case MVT::i64: in emitAddSub()
1150 MVT SrcVT = RetVT; in emitAddSub()
1151 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1281 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr()
1291 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rr()
1300 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rr()
1319 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri()
1324 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_ri()
1342 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_ri()
1364 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs()
1374 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rs()
1387 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rs()
1407 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx()
1417 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rx()
1429 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rx()
1457 MVT VT = EVT.getSimpleVT(); in emitCmp()
1462 case MVT::i1: in emitCmp()
1463 case MVT::i8: in emitCmp()
1464 case MVT::i16: in emitCmp()
1465 case MVT::i32: in emitCmp()
1466 case MVT::i64: in emitCmp()
1468 case MVT::f32: in emitCmp()
1469 case MVT::f64: in emitCmp()
1474 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, in emitICmp()
1480 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri()
1486 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) { in emitFCmp()
1487 if (RetVT != MVT::f32 && RetVT != MVT::f64) in emitFCmp()
1503 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1514 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1521 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, in emitAdd()
1532 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, in emitAdd_ri_()
1551 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS, in emitSub()
1557 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr()
1564 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs()
1574 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp()
1649 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1651 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp()
1652 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp()
1653 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp()
1658 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_ri()
1674 case MVT::i1: in emitLogicalOp_ri()
1675 case MVT::i8: in emitLogicalOp_ri()
1676 case MVT::i16: in emitLogicalOp_ri()
1677 case MVT::i32: { in emitLogicalOp_ri()
1684 case MVT::i64: in emitLogicalOp_ri()
1697 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1698 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_ri()
1699 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_ri()
1704 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_rs()
1725 case MVT::i1: in emitLogicalOp_rs()
1726 case MVT::i8: in emitLogicalOp_rs()
1727 case MVT::i16: in emitLogicalOp_rs()
1728 case MVT::i32: in emitLogicalOp_rs()
1732 case MVT::i64: in emitLogicalOp_rs()
1740 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp_rs()
1741 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_rs()
1742 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_rs()
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri()
1752 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad()
1828 bool IsRet64Bit = RetVT == MVT::i64; in emitLoad()
1832 case MVT::i1: // Intentional fall-through. in emitLoad()
1833 case MVT::i8: in emitLoad()
1838 case MVT::i16: in emitLoad()
1843 case MVT::i32: in emitLoad()
1848 case MVT::i64: in emitLoad()
1852 case MVT::f32: in emitLoad()
1856 case MVT::f64: in emitLoad()
1869 if (VT == MVT::i1) { in emitLoad()
1870 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1); in emitLoad()
1877 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1890 MVT VT; in selectAddSub()
1916 MVT VT; in selectLogicalOp()
1945 MVT VT; in selectLoad()
1975 MVT RetVT = VT; in selectLoad()
2016 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
2023 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, in selectLoad()
2056 bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg, in emitStoreRelease()
2062 case MVT::i8: Opc = AArch64::STLRB; break; in emitStoreRelease()
2063 case MVT::i16: Opc = AArch64::STLRH; break; in emitStoreRelease()
2064 case MVT::i32: Opc = AArch64::STLRW; break; in emitStoreRelease()
2065 case MVT::i64: Opc = AArch64::STLRX; break; in emitStoreRelease()
2078 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, in emitStore()
2121 case MVT::i1: VTIsi1 = true; LLVM_FALLTHROUGH; in emitStore()
2122 case MVT::i8: Opc = OpcTable[Idx][0]; break; in emitStore()
2123 case MVT::i16: Opc = OpcTable[Idx][1]; break; in emitStore()
2124 case MVT::i32: Opc = OpcTable[Idx][2]; break; in emitStore()
2125 case MVT::i64: Opc = OpcTable[Idx][3]; break; in emitStore()
2126 case MVT::f32: Opc = OpcTable[Idx][4]; break; in emitStore()
2127 case MVT::f64: Opc = OpcTable[Idx][5]; break; in emitStore()
2132 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); in emitStore()
2147 MVT VT; in selectStore()
2175 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2178 VT = MVT::getIntegerVT(VT.getSizeInBits()); in selectStore()
2179 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2275 MVT VT; in emitCompareAndBranch()
2321 if (VT == MVT::i1) in emitCompareAndBranch()
2368 SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill, in emitCompareAndBranch()
2372 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true); in emitCompareAndBranch()
2555 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1); in selectCmp()
2667 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2678 MVT VT; in selectSelect()
2687 case MVT::i1: in selectSelect()
2688 case MVT::i8: in selectSelect()
2689 case MVT::i16: in selectSelect()
2690 case MVT::i32: in selectSelect()
2694 case MVT::i64: in selectSelect()
2698 case MVT::f32: in selectSelect()
2702 case MVT::f64: in selectSelect()
2840 MVT DestVT; in selectFPToInt()
2849 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2853 if (SrcVT == MVT::f64) { in selectFPToInt()
2855 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2857 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2860 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2862 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2865 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2873 MVT DestVT; in selectIntToFP()
2877 if (DestVT == MVT::f16) in selectIntToFP()
2880 assert((DestVT == MVT::f32 || DestVT == MVT::f64) && in selectIntToFP()
2891 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
2893 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2900 if (SrcVT == MVT::i64) { in selectIntToFP()
2902 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri; in selectIntToFP()
2904 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri; in selectIntToFP()
2907 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri; in selectIntToFP()
2909 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri; in selectIntToFP()
2953 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
2961 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2963 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2991 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); in fastLowerArguments()
2994 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
2997 VT = MVT::i32; in fastLowerArguments()
2998 } else if (VT == MVT::i64) { in fastLowerArguments()
3001 } else if (VT == MVT::f16) { in fastLowerArguments()
3004 } else if (VT == MVT::f32) { in fastLowerArguments()
3007 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
3030 SmallVectorImpl<MVT> &OutVTs, in processCallArgs()
3048 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs()
3059 MVT DestVT = VA.getLocVT(); in processCallArgs()
3060 MVT SrcVT = ArgVT; in processCallArgs()
3069 MVT DestVT = VA.getLocVT(); in processCallArgs()
3070 MVT SrcVT = ArgVT; in processCallArgs()
3119 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall()
3129 if (RetVT != MVT::isVoid) { in finishCall()
3139 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3186 MVT RetVT; in fastLowerCall()
3188 RetVT = MVT::isVoid; in fastLowerCall()
3198 SmallVector<MVT, 16> OutVTs; in fastLowerCall()
3202 MVT VT; in fastLowerCall()
3204 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3300 MVT VT; in tryEmitSmallMemCpy()
3303 VT = MVT::i64; in tryEmitSmallMemCpy()
3305 VT = MVT::i32; in tryEmitSmallMemCpy()
3307 VT = MVT::i16; in tryEmitSmallMemCpy()
3309 VT = MVT::i8; in tryEmitSmallMemCpy()
3314 VT = MVT::i32; in tryEmitSmallMemCpy()
3316 VT = MVT::i16; in tryEmitSmallMemCpy()
3318 VT = MVT::i8; in tryEmitSmallMemCpy()
3354 MVT RetVT; in foldXALUIntrinsic()
3361 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldXALUIntrinsic()
3533 MVT RetVT; in fastLowerIntrinsicCall()
3537 if (RetVT != MVT::f32 && RetVT != MVT::f64) in fastLowerIntrinsicCall()
3546 bool Is64Bit = RetVT == MVT::f64; in fastLowerIntrinsicCall()
3582 MVT VT; in fastLowerIntrinsicCall()
3590 case MVT::f32: in fastLowerIntrinsicCall()
3593 case MVT::f64: in fastLowerIntrinsicCall()
3615 MVT VT; in fastLowerIntrinsicCall()
3642 MVT VT; in fastLowerIntrinsicCall()
3646 if (VT != MVT::i32 && VT != MVT::i64) in fastLowerIntrinsicCall()
3709 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3710 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3711 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, in fastLowerIntrinsicCall()
3720 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3744 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3745 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3746 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg, in fastLowerIntrinsicCall()
3752 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3855 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
3856 if (RVVT == MVT::f128) in selectRet()
3859 MVT DestVT = VA.getValVT(); in selectRet()
3862 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) in selectRet()
3901 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc()
3902 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc()
3904 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3905 SrcVT != MVT::i8) in selectTrunc()
3907 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc()
3908 DestVT != MVT::i1) in selectTrunc()
3922 if (SrcVT == MVT::i64) { in selectTrunc()
3928 case MVT::i1: in selectTrunc()
3931 case MVT::i8: in selectTrunc()
3934 case MVT::i16: in selectTrunc()
3939 unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill, in selectTrunc()
3942 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask); in selectTrunc()
3955 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext()
3956 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 || in emiti1Ext()
3957 DestVT == MVT::i64) && in emiti1Ext()
3960 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emiti1Ext()
3961 DestVT = MVT::i32; in emiti1Ext()
3964 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); in emiti1Ext()
3966 if (DestVT == MVT::i64) { in emiti1Ext()
3979 if (DestVT == MVT::i64) { in emiti1Ext()
3988 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitMul_rr()
3993 case MVT::i8: in emitMul_rr()
3994 case MVT::i16: in emitMul_rr()
3995 case MVT::i32: in emitMul_rr()
3996 RetVT = MVT::i32; in emitMul_rr()
3998 case MVT::i64: in emitMul_rr()
4003 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
4008 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitSMULL_rr()
4010 if (RetVT != MVT::i64) in emitSMULL_rr()
4018 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitUMULL_rr()
4020 if (RetVT != MVT::i64) in emitUMULL_rr()
4028 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr()
4035 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSL_rr()
4036 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSL_rr()
4037 case MVT::i32: Opc = AArch64::LSLVWr; break; in emitLSL_rr()
4038 case MVT::i64: Opc = AArch64::LSLVXr; break; in emitLSL_rr()
4042 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4044 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSL_rr()
4050 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSL_rr()
4054 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri()
4059 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4060 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
4062 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSL_ri()
4063 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSL_ri()
4065 bool Is64Bit = (RetVT == MVT::i64); in emitLSL_ri()
4121 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4134 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSR_rr()
4141 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSR_rr()
4142 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSR_rr()
4143 case MVT::i32: Opc = AArch64::LSRVWr; break; in emitLSR_rr()
4144 case MVT::i64: Opc = AArch64::LSRVXr; break; in emitLSR_rr()
4148 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4150 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask); in emitLSR_rr()
4151 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSR_rr()
4157 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSR_rr()
4161 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri()
4166 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4167 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4169 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSR_ri()
4170 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSR_ri()
4172 bool Is64Bit = (RetVT == MVT::i64); in emitLSR_ri()
4242 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4255 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitASR_rr()
4262 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break; in emitASR_rr()
4263 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitASR_rr()
4264 case MVT::i32: Opc = AArch64::ASRVWr; break; in emitASR_rr()
4265 case MVT::i64: Opc = AArch64::ASRVXr; break; in emitASR_rr()
4269 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4271 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false); in emitASR_rr()
4272 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitASR_rr()
4278 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitASR_rr()
4282 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri()
4287 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4288 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4290 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitASR_ri()
4291 RetVT == MVT::i64) && "Unexpected return value type."); in emitASR_ri()
4293 bool Is64Bit = (RetVT == MVT::i64); in emitASR_ri()
4351 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4364 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt()
4366 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?"); in emitIntExt()
4372 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && in emitIntExt()
4373 (DestVT != MVT::i32) && (DestVT != MVT::i64)) || in emitIntExt()
4374 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
4375 (SrcVT != MVT::i16) && (SrcVT != MVT::i32))) in emitIntExt()
4384 case MVT::i1: in emitIntExt()
4386 case MVT::i8: in emitIntExt()
4387 if (DestVT == MVT::i64) in emitIntExt()
4393 case MVT::i16: in emitIntExt()
4394 if (DestVT == MVT::i64) in emitIntExt()
4400 case MVT::i32: in emitIntExt()
4401 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?"); in emitIntExt()
4408 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emitIntExt()
4409 DestVT = MVT::i32; in emitIntExt()
4410 else if (DestVT == MVT::i64) { in emitIntExt()
4421 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitIntExt()
4473 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, in optimizeIntExtLoad()
4474 MVT SrcVT) { in optimizeIntExtLoad()
4502 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4530 MVT RetVT; in selectIntExt()
4531 MVT SrcVT; in selectIntExt()
4551 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4586 MVT DestVT = DestEVT.getSimpleVT(); in selectRem()
4587 if (DestVT != MVT::i64 && DestVT != MVT::i32) in selectRem()
4591 bool Is64bit = (DestVT == MVT::i64); in selectRem()
4614 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in selectRem()
4628 MVT VT; in selectMul()
4645 MVT SrcVT = VT; in selectMul()
4649 MVT VT; in selectMul()
4658 MVT VT; in selectMul()
4701 MVT RetVT; in selectShift()
4711 MVT SrcVT = RetVT; in selectShift()
4716 MVT TmpVT; in selectShift()
4725 MVT TmpVT; in selectShift()
4790 MVT RetVT, SrcVT; in selectBitCast()
4798 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4800 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4802 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4804 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()
4812 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4813 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4814 case MVT::f32: RC = &AArch64::FPR32RegClass; break; in selectBitCast()
4815 case MVT::f64: RC = &AArch64::FPR64RegClass; break; in selectBitCast()
4831 MVT RetVT; in selectFRem()
4839 case MVT::f32: in selectFRem()
4842 case MVT::f64: in selectFRem()
4869 MVT VT; in selectSDiv()
4877 if ((VT != MVT::i32 && VT != MVT::i64) || !C || in selectSDiv()
4906 if (VT == MVT::i64) { in selectSDiv()
4921 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4948 MVT PtrVT = TLI.getPointerTy(DL); in getRegForGEPIndex()
4971 MVT VT = TLI.getPointerTy(DL); in selectGetElementPtr()
5040 MVT VT; in selectAtomicCmpXchg()
5048 if (VT == MVT::i32) { in selectAtomicCmpXchg()
5052 } else if (VT == MVT::i64) { in selectAtomicCmpXchg()
5082 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()