206                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
209                          bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
212                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
217                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
226   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
243   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
245   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
252                             bool LHSIsKill, uint64_t Imm);
254                             bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
256   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
1174   bool LHSIsKill = hasTrivialKill(LHS);  in emitAddSub()  local
1183       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,  in emitAddSub()
1186       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,  in emitAddSub()
1190       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,  in emitAddSub()
1206           return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1214     return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1234       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1259           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1277   return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1282                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rr()  argument
1314       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rr()
1320                                         bool LHSIsKill, uint64_t Imm,  in emitAddSub_ri()  argument
1358       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_ri()
1365                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rs()  argument
1401       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rs()
1408                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rx()  argument
1446       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rx()
1480 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitICmp_ri()  argument
1482   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,  in emitICmp_ri()
1500   bool LHSIsKill = hasTrivialKill(LHS);  in emitFCmp()  local
1505         .addReg(LHSReg, getKillRegState(LHSIsKill));  in emitFCmp()
1516       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitFCmp()
1558                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rr()  argument
1560   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rr()
1565                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rs()  argument
1569   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rs()
1594   bool LHSIsKill = hasTrivialKill(LHS);  in emitLogicalOp()  local
1599     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1621       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1637         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1650   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1659                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_ri()  argument
1695       fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,  in emitLogicalOp_ri()
1705                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_rs()  argument
1738       fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitLogicalOp_rs()
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitAnd_ri()  argument
1749   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);  in emitAnd_ri()
3702       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3710         MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3725         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()
3737       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3745         MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3757         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()