Lines Matching refs:IsZExt
204 bool WantResult = true, bool IsZExt = false);
224 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
238 bool IsZExt = false);
242 bool IsZExt = false);
266 uint64_t Imm, bool IsZExt = true);
270 uint64_t Imm, bool IsZExt = true);
274 uint64_t Imm, bool IsZExt = false);
316 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
323 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
1129 bool WantResult, bool IsZExt) { in emitAddSub() argument
1140 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
1144 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
1177 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1181 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue(); in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1452 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) { in emitCmp() argument
1467 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1475 bool IsZExt) { in emitICmp() argument
1477 IsZExt) != 0; in emitICmp()
1522 bool SetFlags, bool WantResult, bool IsZExt) { in emitAdd() argument
1524 IsZExt); in emitAdd()
1552 bool SetFlags, bool WantResult, bool IsZExt) { in emitSub() argument
1554 IsZExt); in emitSub()
3868 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
3869 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
3955 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext() argument
3963 if (IsZExt) { in emiti1Ext()
4056 bool IsZExt) { in emitLSL_ri() argument
4081 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4120 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri()
4163 bool IsZExt) { in emitLSR_ri() argument
4188 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4220 if (Shift >= SrcBits && IsZExt) in emitLSR_ri()
4225 if (!IsZExt) { in emitLSR_ri()
4226 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4232 IsZExt = true; in emitLSR_ri()
4241 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri()
4284 bool IsZExt) { in emitASR_ri() argument
4309 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4341 if (Shift >= SrcBits && IsZExt) in emitASR_ri()
4350 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri()
4365 bool IsZExt) { in emitIntExt() argument
4385 return emiti1Ext(SrcReg, DestVT, IsZExt); in emitIntExt()
4388 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4390 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4395 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4397 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4402 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4490 bool IsZExt = isa<ZExtInst>(I); in optimizeIntExtLoad() local
4498 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4507 if (IsZExt) { in optimizeIntExtLoad()
4548 bool IsZExt = isa<ZExtInst>(I); in selectIntExt() local
4550 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4573 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4646 bool IsZExt = true; in selectMul() local
4652 IsZExt = true; in selectMul()
4661 IsZExt = false; in selectMul()
4673 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4712 bool IsZExt = I->getOpcode() != Instruction::AShr; in selectShift() local
4719 IsZExt = true; in selectShift()
4728 IsZExt = false; in selectShift()
4742 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4745 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4748 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()