234   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
235   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2840   MVT DestVT;  in selectFPToInt()  local
2841   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectFPToInt()
2855       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;  in selectFPToInt()
2857       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;  in selectFPToInt()
2860       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;  in selectFPToInt()
2862       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;  in selectFPToInt()
2865       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2873   MVT DestVT;  in selectIntToFP()  local
2874   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectIntToFP()
2877   if (DestVT == MVT::f16)  in selectIntToFP()
2880   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&  in selectIntToFP()
2902       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;  in selectIntToFP()
2904       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;  in selectIntToFP()
2907       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;  in selectIntToFP()
2909       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;  in selectIntToFP()
2912   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,  in selectIntToFP()
3059       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3061       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3069       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3071       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3859     MVT DestVT = VA.getValVT();  in selectRet()  local
3861     if (RVVT != DestVT) {  in selectRet()
3869       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3902   MVT DestVT = DestEVT.getSimpleVT();  in selectTrunc()  local
3907   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&  in selectTrunc()
3908       DestVT != MVT::i1)  in selectTrunc()
3924     switch (DestVT.SimpleTy) {  in selectTrunc()
3955 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()  argument
3956   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||  in emiti1Ext()
3957           DestVT == MVT::i64) &&  in emiti1Ext()
3960   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emiti1Ext()
3961     DestVT = MVT::i32;  in emiti1Ext()
3966     if (DestVT == MVT::i64) {  in emiti1Ext()
3979     if (DestVT == MVT::i64) {  in emiti1Ext()
4364 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4366   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");  in emitIntExt()
4372   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&  in emitIntExt()
4373        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||  in emitIntExt()
4385     return emiti1Ext(SrcReg, DestVT, IsZExt);  in emitIntExt()
4387     if (DestVT == MVT::i64)  in emitIntExt()
4394     if (DestVT == MVT::i64)  in emitIntExt()
4401     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");  in emitIntExt()
4408   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emitIntExt()
4409     DestVT = MVT::i32;  in emitIntExt()
4410   else if (DestVT == MVT::i64) {  in emitIntExt()
4421       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4586   MVT DestVT = DestEVT.getSimpleVT();  in selectRem()  local
4587   if (DestVT != MVT::i64 && DestVT != MVT::i32)  in selectRem()
4591   bool Is64bit = (DestVT == MVT::i64);  in selectRem()
4614       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()