Lines Matching refs:addOperand
656 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
657 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
665 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
666 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
670 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
671 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
675 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
676 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
720 MovZ.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
721 MovZ.addOperand(Hi_MCSym); in EmitInstruction()
722 MovZ.addOperand(MCOperand::createImm(16)); in EmitInstruction()
727 MovK.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
728 MovK.addOperand(MCOperand::createReg(DestReg)); in EmitInstruction()
729 MovK.addOperand(Lo_MCSym); in EmitInstruction()
730 MovK.addOperand(MCOperand::createImm(0)); in EmitInstruction()
741 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
742 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm())); in EmitInstruction()
779 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
788 TmpInst.addOperand(Dest); in EmitInstruction()
811 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
812 Adrp.addOperand(SymTLSDesc); in EmitInstruction()
817 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()
818 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
819 Ldr.addOperand(SymTLSDescLo12); in EmitInstruction()
820 Ldr.addOperand(MCOperand::createImm(0)); in EmitInstruction()
825 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
826 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
827 Add.addOperand(SymTLSDescLo12); in EmitInstruction()
828 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); in EmitInstruction()
835 TLSDescCall.addOperand(Sym); in EmitInstruction()
840 Blr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()