Lines Matching refs:virtReg
84 void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) { in assignVirt2Phys() argument
85 assert(TargetRegisterInfo::isVirtualRegister(virtReg) && in assignVirt2Phys()
87 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && in assignVirt2Phys()
92 Virt2PhysMap[virtReg] = physReg; in assignVirt2Phys()
121 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { in assignVirt2StackSlot() argument
122 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()
123 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()
125 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
126 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC); in assignVirt2StackSlot()
129 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { in assignVirt2StackSlot() argument
130 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()
131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()
136 Virt2StackSlotMap[virtReg] = SS; in assignVirt2StackSlot()