402   if (Op.getValueType().isVector())  in ShrinkDemandedOp()
455   APInt DemandedElts = VT.isVector()  in SimplifyDemandedBits()
478   assert((!Op.getValueType().isVector() ||  in SimplifyDemandedBits()
1044         if (TLO.LegalTypes() && !ShiftAmtTy.isVector())  in SimplifyDemandedBits()
1279     if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() &&  in SimplifyDemandedBits()
1304     if (SrcVT.isVector() && NumSrcEltBits > 1 &&  in SimplifyDemandedBits()
1444   assert(VT.isVector() && "Expected vector op");  in SimplifyDemandedVectorElts()
1488     if (!SrcVT.isVector())  in SimplifyDemandedVectorElts()
2627       if (!VT.isVector()) { // TODO: Support this for vectors.  in SimplifySetCC()
2648       if (!VT.isVector()) { // TODO: Support this for vectors.  in SimplifySetCC()
2667       if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {  in SimplifySetCC()
2685       if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {  in SimplifySetCC()
2701     if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {  in SimplifySetCC()
3729   if (VT.isVector()) {  in BuildExactSDIV()
3824   if (VT.isVector()) {  in BuildSDIV()
3942   if (VT.isVector()) {  in BuildUDIV()
3984     if (VT.isVector())  in BuildUDIV()
4091   if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&  in expandMUL_LOHI()
4221   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||  in expandFunnelShift()
4286   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||  in expandROT()
4384   if (DstVT.isVector() && (!isOperationLegalOrCustom(ISD::FP_TO_SINT, DstVT) ||  in expandFP_TO_UINT()
4451     if (SrcVT.isVector() &&  in expandUINT_TO_FP()
4488     if (SrcVT.isVector() &&  in expandUINT_TO_FP()
4564   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) ||  in expandCTPOP()
4638   if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||  in expandCTLZ()
4690   if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||  in expandCTTZ()
4726   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) ||  in expandABS()
4862   if (VT.isFloatingPoint() || VT.isVector()) {  in expandUnalignedLoad()
4866           LoadedVT.isVector()) {  in expandUnalignedLoad()
4951   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&  in expandUnalignedLoad()
5019   if (MemVT.isFloatingPoint() || MemVT.isVector()) {  in expandUnalignedStore()
5023           MemVT.isVector()) {  in expandUnalignedStore()
5104          !ST->getMemoryVT().isVector() &&  in expandUnalignedStore()
5291   if (VT.isVector()) {  in expandAddSubSat()