227     Topo.AddPred(SU, D.getSUnit());  in AddPred()
235     Topo.RemovePred(SU, D.getSUnit());  in RemovePred()
394   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()
559       assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&  in ReleasePredecessors()
561       LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
815   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()
837       assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&  in UnscheduleNodeBottomUp()
893         LiveRegGens[Reg] = Succ.getSUnit();  in UnscheduleNodeBottomUp()
896               Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())  in UnscheduleNodeBottomUp()
897             LiveRegGens[Reg] = Succ2.getSUnit();  in UnscheduleNodeBottomUp()
1058     else if (isOperandOf(Pred.getSUnit(), LoadNode))  in TryUnfoldSU()
1086     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1097     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1190     SUnit *SuccSU = Succ.getSUnit();  in CopyAndMoveSuccessors()
1229     SUnit *SuccSU = Succ.getSUnit();  in InsertCopiesAndMoveSuccs()
1346       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),  in DelayForLiveRegsBottomUp()
1946       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
1969       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
2073     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()
2122     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()
2165     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()
2247     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()
2314     unsigned Height = Succ.getSUnit()->getHeight();  in closestSucc()
2317     if (Succ.getSUnit()->getNode() &&  in closestSucc()
2318         Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)  in closestSucc()
2319       Height = closestSucc(Succ.getSUnit())+1;  in closestSucc()
2343     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()
2365     const SUnit *SuccSU = Succ.getSUnit();  in hasOnlyLiveOutUses()
2402     Pred.getSUnit()->isVRegCycle = true;  in initVRegCycle()
2414     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()
2418       Pred.getSUnit()->isVRegCycle = false;  in resetVRegCycle()
2432     if (Pred.getSUnit()->isVRegCycle &&  in hasVRegCycleUse()
2433         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasVRegCycleUse()
2831     SUnit *SuccSU = Succ.getSUnit();  in canClobberReachingPhysRegUse()
2838           scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2847               scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2946         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
2968       SUnit *PredSuccSU = PredSucc.getSUnit();  in PrescheduleNodesWithMultipleUses()
2992       SUnit *SuccSU = Edge.getSUnit();  in PrescheduleNodesWithMultipleUses()
3039         SUnit *SuccSU = Succ.getSUnit();  in AddPseudoTwoAddrDeps()
3055           SuccSU = SuccSU->Succs.front().getSUnit();  in AddPseudoTwoAddrDeps()