Lines Matching refs:SUnit
151 std::vector<SUnit *> PendingQueue;
170 std::unique_ptr<SUnit*[]> LiveRegDefs;
171 std::unique_ptr<SUnit*[]> LiveRegGens;
175 SmallVector<SUnit*, 4> Interferences;
177 using LRegsMapT = DenseMap<SUnit *, SmallVector<unsigned, 4>>;
187 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
213 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
219 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
226 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
234 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
240 bool isReady(SUnit *SU) { in isReady()
245 void ReleasePred(SUnit *SU, const SDep *PredEdge);
246 void ReleasePredecessors(SUnit *SU);
249 void AdvancePastStalls(SUnit *SU);
250 void EmitNode(SUnit *SU);
251 void ScheduleNodeBottomUp(SUnit*);
253 void UnscheduleNodeBottomUp(SUnit*);
255 void BacktrackBottomUp(SUnit*, SUnit*);
256 SUnit *TryUnfoldSU(SUnit *);
257 SUnit *CopyAndMoveSuccessors(SUnit*);
258 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
261 SmallVectorImpl<SUnit*>&);
262 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
266 SUnit *PickNodeToScheduleBottomUp();
271 SUnit *CreateNewSUnit(SDNode *N) { in CreateNewSUnit()
273 SUnit *NewNode = newSUnit(N); in CreateNewSUnit()
282 SUnit *CreateClone(SUnit *N) { in CreateClone()
284 SUnit *NewNode = Clone(N); in CreateClone()
360 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
361 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
393 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
394 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
549 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors()
558 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors()
582 SUnit *Def = &SUnits[N->getNodeId()]; in ReleasePredecessors()
646 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls()
688 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode()
725 static void resetVRegCycle(SUnit *SU);
730 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp()
815 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
829 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp()
853 SUnit *SeqEnd = CallSeqEndForStart[SU]; in UnscheduleNodeBottomUp()
929 std::vector<SUnit *>::const_iterator I = (Sequence.end() - LookAhead); in RestoreHazardCheckerBottomUp()
932 SUnit *SU = *I; in RestoreHazardCheckerBottomUp()
942 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp()
943 SUnit *OldSU = Sequence.back(); in BacktrackBottomUp()
964 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf()
974 SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { in TryUnfoldSU()
997 SUnit *LoadSU; in TryUnfoldSU()
1014 SUnit *NewSU; in TryUnfoldSU()
1086 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1097 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1127 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors()
1144 SUnit *NewSU; in CopyAndMoveSuccessors()
1166 SUnit *UnfoldSU = TryUnfoldSU(SU); in CopyAndMoveSuccessors()
1186 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in CopyAndMoveSuccessors()
1190 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
1211 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs()
1214 SmallVectorImpl<SUnit*> &Copies) { in InsertCopiesAndMoveSuccs()
1215 SUnit *CopyFromSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1219 SUnit *CopyToSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1225 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in InsertCopiesAndMoveSuccs()
1229 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
1286 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, in CheckForLiveRegDef()
1287 SUnit **LiveRegDefs, in CheckForLiveRegDef()
1308 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked()
1309 ArrayRef<SUnit*> LiveRegDefs, in CheckForLiveRegDefMasked()
1335 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp()
1425 SUnit *SU = Interferences[i-1]; in releaseInterferences()
1451 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { in PickNodeToScheduleBottomUp()
1452 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); in PickNodeToScheduleBottomUp()
1483 for (SUnit *TrySU : Interferences) { in PickNodeToScheduleBottomUp()
1488 SUnit *BtSU = nullptr; in PickNodeToScheduleBottomUp()
1534 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp()
1538 SUnit *LRDef = LiveRegDefs[Reg]; in PickNodeToScheduleBottomUp()
1551 SUnit *NewDef = nullptr; in PickNodeToScheduleBottomUp()
1559 SmallVector<SUnit*, 2> Copies; in PickNodeToScheduleBottomUp()
1586 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; in ListScheduleBottomUp()
1601 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp()
1628 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1638 bool operator()(SUnit* left, SUnit* right) const { in operator ()()
1658 bool operator()(SUnit* left, SUnit* right) const;
1672 bool operator()(SUnit* left, SUnit* right) const;
1686 bool isReady(SUnit *SU, unsigned CurCycle) const;
1688 bool operator()(SUnit* left, SUnit* right) const;
1703 bool isReady(SUnit *SU, unsigned CurCycle) const;
1705 bool operator()(SUnit* left, SUnit* right) const;
1710 std::vector<SUnit *> Queue;
1716 std::vector<SUnit> *SUnits;
1763 void initNodes(std::vector<SUnit> &sunits) override;
1765 void addNode(const SUnit *SU) override;
1767 void updateNode(const SUnit *SU) override;
1775 unsigned getNodePriority(const SUnit *SU) const;
1777 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1785 void push(SUnit *U) override { in push()
1791 void remove(SUnit *SU) override { in remove()
1794 std::vector<SUnit *>::iterator I = llvm::find(Queue, SU); in remove()
1805 bool HighRegPressure(const SUnit *SU) const;
1807 bool MayReduceRegPressure(SUnit *SU) const;
1809 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1811 void scheduledNode(SUnit *SU) override;
1813 void unscheduledNode(SUnit *SU) override;
1816 bool canClobber(const SUnit *SU, const SUnit *Op);
1823 static SUnit *popFromQueueImpl(std::vector<SUnit *> &Q, SF &Picker) { in popFromQueueImpl()
1824 std::vector<SUnit *>::iterator Best = Q.begin(); in popFromQueueImpl()
1828 SUnit *V = *Best; in popFromQueueImpl()
1836 SUnit *popFromQueue(std::vector<SUnit *> &Q, SF &Picker, ScheduleDAG *DAG) { in popFromQueue()
1871 bool isReady(SUnit *U) const override { in isReady()
1875 SUnit *pop() override { in pop()
1878 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); in pop()
1886 std::vector<SUnit *> DumpQueue = Queue; in dump()
1889 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump()
1914 static int checkSpecialNodes(const SUnit *left, const SUnit *right) { in checkSpecialNodes()
1925 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber()
1931 WorkState(const SUnit *SU) : SU(SU) {} in CalcNodeSethiUllmanNumber()
1932 const SUnit *SU; in CalcNodeSethiUllmanNumber()
1946 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
1969 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
1995 for (const SUnit &SU : *SUnits) in CalculateSethiUllmanNumbers()
1999 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode()
2006 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode()
2013 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
2066 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
2073 SUnit *PredSU = Pred.getSUnit(); in HighRegPressure()
2091 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
2116 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff()
2122 SUnit *PredSU = Pred.getSUnit(); in RegPressureDiff()
2155 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode()
2165 SUnit *PredSU = Pred.getSUnit(); in scheduledNode()
2224 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode()
2247 SUnit *PredSU = Pred.getSUnit(); in unscheduledNode()
2310 static unsigned closestSucc(const SUnit *SU) { in closestSucc()
2328 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches()
2339 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers()
2343 const SUnit *PredSU = Pred.getSUnit(); in hasOnlyLiveInOpers()
2361 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses()
2365 const SUnit *SuccSU = Succ.getSUnit(); in hasOnlyLiveOutUses()
2389 static void initVRegCycle(SUnit *SU) { in initVRegCycle()
2408 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle()
2414 SUnit *PredSU = Pred.getSUnit(); in resetVRegCycle()
2425 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse()
2444 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall()
2454 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, in BUCompareLatency()
2505 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { in BURRSort()
2609 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2617 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2636 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2651 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2683 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2693 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing()
2717 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2778 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { in initNodes()
2791 for (SUnit &SU : sunits) in initNodes()
2799 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber()
2820 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse()
2831 SUnit *SuccSU = Succ.getSUnit(); in canClobberReachingPhysRegUse()
2856 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs()
2925 for (SUnit &SU : *SUnits) { in PrescheduleNodesWithMultipleUses()
2943 SUnit *PredSU = nullptr; in PrescheduleNodesWithMultipleUses()
2968 SUnit *PredSuccSU = PredSucc.getSUnit(); in PrescheduleNodesWithMultipleUses()
2992 SUnit *SuccSU = Edge.getSUnit(); in PrescheduleNodesWithMultipleUses()
3014 for (SUnit &SU : *SUnits) { in AddPseudoTwoAddrDeps()
3033 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; in AddPseudoTwoAddrDeps()
3039 SUnit *SuccSU = Succ.getSUnit(); in AddPseudoTwoAddrDeps()