394   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()  local
397   if (PredSU->NumSuccsLeft == 0) {  in ReleasePred()
399     dumpNode(*PredSU);  in ReleasePred()
404   --PredSU->NumSuccsLeft;  in ReleasePred()
409     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());  in ReleasePred()
414   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {  in ReleasePred()
415     PredSU->isAvailable = true;  in ReleasePred()
417     unsigned Height = PredSU->getHeight();  in ReleasePred()
421     if (isReady(PredSU)) {  in ReleasePred()
422       AvailableQueue->push(PredSU);  in ReleasePred()
426     else if (!PredSU->isPending) {  in ReleasePred()
427       PredSU->isPending = true;  in ReleasePred()
428       PendingQueue.push_back(PredSU);  in ReleasePred()
815   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()  local
816   if (PredSU->isAvailable) {  in CapturePred()
817     PredSU->isAvailable = false;  in CapturePred()
818     if (!PredSU->isPending)  in CapturePred()
819       AvailableQueue->remove(PredSU);  in CapturePred()
822   assert(PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&  in CapturePred()
824   ++PredSU->NumSuccsLeft;  in CapturePred()
1946       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()  local
1947       if (SUNumbers[PredSU->NodeNum] == 0) {  in CalcNodeSethiUllmanNumber()
1951           assert(It.SU != PredSU && "Trying to push an element twice?");  in CalcNodeSethiUllmanNumber()
1955         WorkList.push_back(PredSU);  in CalcNodeSethiUllmanNumber()
1969       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()  local
1970       unsigned PredSethiUllman = SUNumbers[PredSU->NodeNum];  in CalcNodeSethiUllmanNumber()
2073     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()  local
2076     if (PredSU->NumRegDefsLeft == 0) {  in HighRegPressure()
2079     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in HighRegPressure()
2122     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()  local
2125     if (PredSU->NumRegDefsLeft == 0) {  in RegPressureDiff()
2126       if (PredSU->getNode()->isMachineOpcode())  in RegPressureDiff()
2130     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in RegPressureDiff()
2165     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()  local
2168     if (PredSU->NumRegDefsLeft == 0) {  in scheduledNode()
2186     --PredSU->NumRegDefsLeft;  in scheduledNode()
2187     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;  in scheduledNode()
2188     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in scheduledNode()
2247     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()  local
2250     if (PredSU->NumSuccsLeft != PredSU->Succs.size())  in unscheduledNode()
2252     const SDNode *PN = PredSU->getNode();  in unscheduledNode()
2343     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()  local
2344     if (PredSU->getNode() &&  in hasOnlyLiveInOpers()
2345         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasOnlyLiveInOpers()
2347         cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveInOpers()
2414     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()  local
2415     if (PredSU->isVRegCycle) {  in resetVRegCycle()
2416       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&  in resetVRegCycle()
2943     SUnit *PredSU = nullptr;  in PrescheduleNodesWithMultipleUses()  local
2946         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
2949     assert(PredSU);  in PrescheduleNodesWithMultipleUses()
2953     if (PredSU->hasPhysRegDefs)  in PrescheduleNodesWithMultipleUses()
2956     if (PredSU->NumSuccs == 1)  in PrescheduleNodesWithMultipleUses()
2967     for (const SDep &PredSucc : PredSU->Succs) {  in PrescheduleNodesWithMultipleUses()
2987                << PredSU->NodeNum  in PrescheduleNodesWithMultipleUses()
2989     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {  in PrescheduleNodesWithMultipleUses()
2990       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
2994         Edge.setSUnit(PredSU);  in PrescheduleNodesWithMultipleUses()