551   for (SDep &Pred : SU->Preds) {  in ReleasePredecessors()
552     ReleasePred(SU, &Pred);  in ReleasePredecessors()
553     if (Pred.isAssignedRegDep()) {  in ReleasePredecessors()
558       SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef;  in ReleasePredecessors()
559       assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&  in ReleasePredecessors()
561       LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
562       if (!LiveRegGens[Pred.getReg()]) {  in ReleasePredecessors()
564         LiveRegGens[Pred.getReg()] = SU;  in ReleasePredecessors()
833   for (SDep &Pred : SU->Preds) {  in UnscheduleNodeBottomUp()
834     CapturePred(&Pred);  in UnscheduleNodeBottomUp()
835     if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){  in UnscheduleNodeBottomUp()
837       assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&  in UnscheduleNodeBottomUp()
840       LiveRegDefs[Pred.getReg()] = nullptr;  in UnscheduleNodeBottomUp()
841       LiveRegGens[Pred.getReg()] = nullptr;  in UnscheduleNodeBottomUp()
842       releaseInterferences(Pred.getReg());  in UnscheduleNodeBottomUp()
1055   for (SDep &Pred : SU->Preds) {  in TryUnfoldSU()
1056     if (Pred.isCtrl())  in TryUnfoldSU()
1057       ChainPreds.push_back(Pred);  in TryUnfoldSU()
1058     else if (isOperandOf(Pred.getSUnit(), LoadNode))  in TryUnfoldSU()
1059       LoadPreds.push_back(Pred);  in TryUnfoldSU()
1061       NodePreds.push_back(Pred);  in TryUnfoldSU()
1071   for (const SDep &Pred : ChainPreds) {  in TryUnfoldSU()  local
1072     RemovePred(SU, Pred);  in TryUnfoldSU()
1074       AddPred(LoadSU, Pred);  in TryUnfoldSU()
1076   for (const SDep &Pred : LoadPreds) {  in TryUnfoldSU()  local
1077     RemovePred(SU, Pred);  in TryUnfoldSU()
1079       AddPred(LoadSU, Pred);  in TryUnfoldSU()
1081   for (const SDep &Pred : NodePreds) {  in TryUnfoldSU()  local
1082     RemovePred(SU, Pred);  in TryUnfoldSU()
1083     AddPred(NewSU, Pred);  in TryUnfoldSU()
1180   for (SDep &Pred : SU->Preds)  in CopyAndMoveSuccessors()
1181     if (!Pred.isArtificial())  in CopyAndMoveSuccessors()
1182       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
1344   for (SDep &Pred : SU->Preds) {  in DelayForLiveRegsBottomUp()
1345     if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU)  in DelayForLiveRegsBottomUp()
1346       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),  in DelayForLiveRegsBottomUp()
1944       auto &Pred = TempSU->Preds[P];  in CalcNodeSethiUllmanNumber()  local
1945       if (Pred.isCtrl()) continue;  // ignore chain preds  in CalcNodeSethiUllmanNumber()
1946       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
1967     for (const SDep &Pred : TempSU->Preds) {  in CalcNodeSethiUllmanNumber()  local
1968       if (Pred.isCtrl()) continue;  // ignore chain preds  in CalcNodeSethiUllmanNumber()
1969       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
2070   for (const SDep &Pred : SU->Preds) {  in HighRegPressure()  local
2071     if (Pred.isCtrl())  in HighRegPressure()
2073     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()
2119   for (const SDep &Pred : SU->Preds) {  in RegPressureDiff()  local
2120     if (Pred.isCtrl())  in RegPressureDiff()
2122     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()
2162   for (const SDep &Pred : SU->Preds) {  in scheduledNode()  local
2163     if (Pred.isCtrl())  in scheduledNode()
2165     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()
2244   for (const SDep &Pred : SU->Preds) {  in unscheduledNode()  local
2245     if (Pred.isCtrl())  in unscheduledNode()
2247     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()
2330   for (const SDep &Pred : SU->Preds) {  in calcMaxScratches()  local
2331     if (Pred.isCtrl()) continue;  // ignore chain preds  in calcMaxScratches()
2341   for (const SDep &Pred : SU->Preds) {  in hasOnlyLiveInOpers()  local
2342     if (Pred.isCtrl()) continue;  in hasOnlyLiveInOpers()
2343     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()
2400   for (const SDep &Pred : SU->Preds) {  in initVRegCycle()  local
2401     if (Pred.isCtrl()) continue;  in initVRegCycle()
2402     Pred.getSUnit()->isVRegCycle = true;  in initVRegCycle()
2412   for (const SDep &Pred : SU->Preds) {  in resetVRegCycle()  local
2413     if (Pred.isCtrl()) continue;  // ignore chain preds  in resetVRegCycle()
2414     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()
2418       Pred.getSUnit()->isVRegCycle = false;  in resetVRegCycle()
2430   for (const SDep &Pred : SU->Preds) {  in hasVRegCycleUse()  local
2431     if (Pred.isCtrl()) continue;  // ignore chain preds  in hasVRegCycleUse()
2432     if (Pred.getSUnit()->isVRegCycle &&  in hasVRegCycleUse()
2433         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasVRegCycleUse()
2944     for (const SDep &Pred : SU.Preds)  in PrescheduleNodesWithMultipleUses()  local
2945       if (!Pred.isCtrl()) {  in PrescheduleNodesWithMultipleUses()
2946         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()