163   for (SDep &Pred : SU->Preds) {  in ReleasePredecessors()
164     ReleasePred(SU, &Pred);  in ReleasePredecessors()
165     if (Pred.isAssignedRegDep()) {  in ReleasePredecessors()
170       if (!LiveRegDefs[Pred.getReg()]) {  in ReleasePredecessors()
172         LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
173         LiveRegCycles[Pred.getReg()] = CurCycle;  in ReleasePredecessors()
283     for (SDep &Pred : SU->Preds) {  in CopyAndMoveSuccessors()
284       if (Pred.isCtrl())  in CopyAndMoveSuccessors()
285         ChainPred = Pred;  in CopyAndMoveSuccessors()
286       else if (Pred.getSUnit()->getNode() &&  in CopyAndMoveSuccessors()
287                Pred.getSUnit()->getNode()->isOperandOf(LoadNode))  in CopyAndMoveSuccessors()
288         LoadPreds.push_back(Pred);  in CopyAndMoveSuccessors()
290         NodePreds.push_back(Pred);  in CopyAndMoveSuccessors()
305       const SDep &Pred = LoadPreds[i];  in CopyAndMoveSuccessors()  local
306       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
308         AddPred(LoadSU, Pred);  in CopyAndMoveSuccessors()
312       const SDep &Pred = NodePreds[i];  in CopyAndMoveSuccessors()  local
313       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
314       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
353   for (SDep &Pred : SU->Preds)  in CopyAndMoveSuccessors()
354     if (!Pred.isArtificial())  in CopyAndMoveSuccessors()
355       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
475   for (SDep &Pred : SU->Preds) {  in DelayForLiveRegsBottomUp()
476     if (Pred.isAssignedRegDep()) {  in DelayForLiveRegsBottomUp()
477       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,  in DelayForLiveRegsBottomUp()