628   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBinaryOp()  local
649                                       Op0IsKill, Imm, VT.getSimpleVT());  in selectBinaryOp()
665                                    ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);  in selectBinaryOp()
1550   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBitCast()  local
1567     ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);  in selectBitCast()
1968                                 bool Op0IsKill, uint64_t Imm, MVT ImmType) {  in fastEmit_ri_()  argument
1986   unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);  in fastEmit_ri_()
2007   return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill);  in fastEmit_ri_()
2042                                   bool Op0IsKill) {  in fastEmitInst_r()  argument
2050         .addReg(Op0, getKillRegState(Op0IsKill));  in fastEmitInst_r()
2053         .addReg(Op0, getKillRegState(Op0IsKill));  in fastEmitInst_r()
2063                                    bool Op0IsKill, unsigned Op1,  in fastEmitInst_rr()  argument
2073         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rr()
2077         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rr()
2087                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rrr()  argument
2099         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrr()
2104         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrr()
2115                                    bool Op0IsKill, uint64_t Imm) {  in fastEmitInst_ri()  argument
2123         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_ri()
2127         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_ri()
2137                                     bool Op0IsKill, uint64_t Imm1,  in fastEmitInst_rii()  argument
2146         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rii()
2151         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rii()
2181                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rri()  argument
2191         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rri()
2196         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rri()
2222                                               bool Op0IsKill, uint32_t Idx) {  in fastEmitInst_extractsubreg()  argument
2229           ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);  in fastEmitInst_extractsubreg()
2235 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {  in fastEmitZExtFromI1()  argument
2236   return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);  in fastEmitZExtFromI1()