Lines Matching refs:getOpcode
178 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
183 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
702 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
708 if (!(Op.getOpcode() == ISD::FP_EXTEND && in isNegatibleForFree()
715 switch (Op.getOpcode()) { in isNegatibleForFree()
773 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
779 switch (Op.getOpcode()) { in GetNegatedExpression()
816 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
822 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
829 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
856 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
863 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
904 if (N.getOpcode() != ISD::BUILD_VECTOR) in isConstantOrConstantVector()
921 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
934 if (N0.getOpcode() == Opc && !N0->getFlags().hasVectorReduction()) { in ReassociateOps()
954 if (N1.getOpcode() == Opc && !N1->getFlags().hasVectorReduction()) { in ReassociateOps()
1100 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1167 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1232 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1266 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1282 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1295 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1313 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1454 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1455 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1485 switch (N->getOpcode()) { in visit()
1604 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
1607 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
1608 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
1620 switch (N->getOpcode()) { in combine()
1649 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) && in combine()
1657 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
1711 switch (Op.getOpcode()) { in visitTokenFactor()
1794 switch (CurNode->getOpcode()) { in visitTokenFactor()
1879 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
1884 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
1902 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
1947 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
1953 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
1957 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
1961 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
1969 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
1988 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
1993 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
1997 if (!C || ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2062 if (N0.getOpcode() == ISD::SUB && in visitADD()
2074 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADD()
2087 if (N0.getOpcode() == ISD::OR && in visitADD()
2104 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) in visitADD()
2108 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitADD()
2112 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADD()
2116 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADD()
2120 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADD()
2126 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADD()
2132 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADD()
2133 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADD()
2135 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), in visitADD()
2139 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { in visitADD()
2180 unsigned Opcode = N->getOpcode(); in visitADDSAT()
2227 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2232 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
2245 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2246 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
2265 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLike()
2272 if (N1.getOpcode() == ISD::AND) { in visitADDLike()
2284 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLike()
2292 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLike()
2302 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLike()
2364 if (V.getOpcode() != ISD::XOR) return false; in isBooleanFlip()
2432 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
2462 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
2522 if ((N0.getOpcode() == ISD::ADD || in visitADDCARRYLike()
2523 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) && in visitADDCARRYLike()
2548 if (Y.getOpcode() == ISD::UADDO && in visitADDCARRYLike()
2550 CarryIn.getOpcode() == ISD::ADDCARRY && in visitADDCARRYLike()
2621 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
2624 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
2650 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
2654 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
2658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
2662 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
2666 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
2676 if (N0.getOpcode() == ISD::ADD && in visitSUB()
2677 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
2678 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
2680 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), in visitSUB()
2684 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
2690 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
2696 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) in visitSUB()
2702 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { in visitSUB()
2703 if (N1.getOperand(0).getOpcode() == ISD::SUB && in visitSUB()
2710 if (N1.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
2733 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
2749 if (N1C && GA->getOpcode() == ISD::GlobalAddress) in visitSUB()
2761 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
2772 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
2810 return DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, N0.getNode(), in visitSUBSAT()
2887 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
3030 if (N0.getOpcode() == ISD::SHL && in visitMUL()
3044 if (N0.getOpcode() == ISD::SHL && in visitMUL()
3048 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
3062 N0.getOpcode() == ISD::ADD && in visitMUL()
3102 unsigned Opcode = Node->getOpcode(); in useDivRem()
3138 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
3144 unsigned UserOpc = User->getOpcode(); in useDivRem()
3174 unsigned Opc = N->getOpcode(); in simplifyDivRem()
3432 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
3460 unsigned Opcode = N->getOpcode(); in visitREM()
3499 if (N1.getOpcode() == ISD::SHL && in visitREM()
3677 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
3687 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
3790 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C); in visitIMINMAX()
3795 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitIMINMAX()
3799 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
3824 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
3825 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
3828 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
4116 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
4151 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitANDLike()
4327 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
4336 switch(Op.getOpcode()) { in SearchForAndLoads()
4360 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
4433 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
4457 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
4477 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
4493 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
4590 if (N0.getOpcode() == ISD::OR && in visitAND()
4594 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
4618 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
4620 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
4622 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
4623 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
4721 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD || in visitAND()
4722 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
4723 N0.getOperand(0).getOpcode() == ISD::LOAD))) { in visitAND()
4725 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND in visitAND()
4747 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
4758 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
4761 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
4764 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
4815 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
4842 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
4844 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
4846 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
4859 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
4869 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
4871 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
4885 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
4896 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
4950 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
4955 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
5049 if (N0.getOpcode() != ISD::OR) in MatchBSwapHWord()
5055 if (N1.getOpcode() == ISD::OR && in MatchBSwapHWord()
5075 if (N00.getOpcode() != ISD::OR) in MatchBSwapHWord()
5119 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
5145 if (N0.getOpcode() == ISD::AND && in visitORLike()
5146 N1.getOpcode() == ISD::AND && in visitORLike()
5295 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && in visitOR()
5306 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
5325 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
5337 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
5370 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && in extractShiftForRotate()
5383 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
5384 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
5391 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
5392 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
5399 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
5501 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) { in matchRotateSub()
5514 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
5523 if (MaskLoBits && Pos.getOpcode() == ISD::AND) { in matchRotateSub()
5555 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
5610 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
5660 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
5664 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
5716 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
5717 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
5718 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
5719 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
5720 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
5721 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
5722 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
5723 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
5803 switch (Op.getOpcode()) { in calculateByteProvider()
5843 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
5903 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
6052 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
6064 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
6067 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
6167 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
6255 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
6296 if (N0Opcode == N1.getOpcode()) in visitXOR()
6327 switch (LHS->getOpcode()) { in visitShiftByConstant()
6337 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
6350 bool isShift = BinOpLHSVal->getOpcode() == ISD::SHL || in visitShiftByConstant()
6351 BinOpLHSVal->getOpcode() == ISD::SRA || in visitShiftByConstant()
6352 BinOpLHSVal->getOpcode() == ISD::SRL; in visitShiftByConstant()
6353 bool isCopyOrSelect = BinOpLHSVal->getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
6354 BinOpLHSVal->getOpcode() == ISD::SELECT; in visitShiftByConstant()
6369 if (N->getOpcode() == ISD::SRA) { in visitShiftByConstant()
6379 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)), in visitShiftByConstant()
6385 SDValue NewShift = DAG.getNode(N->getOpcode(), in visitShiftByConstant()
6390 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS); in visitShiftByConstant()
6394 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
6395 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
6437 return DAG.getNode(N->getOpcode(), dl, VT, N0, in visitRotate()
6443 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
6444 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
6446 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
6449 unsigned NextOp = N0.getOpcode(); in visitRotate()
6456 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
6464 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
6490 if (N0.getOpcode() == ISD::AND) { in visitSHL()
6495 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
6521 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
6522 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
6531 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
6562 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
6563 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
6564 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
6565 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
6582 DAG.getNode(N0.getOpcode(), DL, VT, N0Op0->getOperand(0)), in visitSHL()
6591 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
6592 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
6614 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) && in visitSHL()
6623 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), in visitSHL()
6632 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && in visitSHL()
6659 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
6671 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
6680 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); in visitSHL()
6684 if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse() && in visitSHL()
6731 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { in visitSRA()
6745 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
6776 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
6812 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
6813 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
6820 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
6821 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
6822 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
6888 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
6915 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
6916 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
6938 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && in visitSRL()
6948 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
6974 if (N0.getOpcode() == ISD::SRA) in visitSRL()
6979 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
7016 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
7017 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
7054 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
7056 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { in visitSRL()
7059 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
7072 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
7086 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, in visitFunnelShift()
7110 if (N0.getOpcode() == ISD::ABS) in visitABS()
7126 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
7139 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
7413 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
7423 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
7434 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
7451 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
7476 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
7496 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
7540 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); in SplitVSETCC()
7541 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); in SplitVSETCC()
7555 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
7556 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
7557 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
7614 if (Mask.getOpcode() != ISD::SETCC) in visitMSCATTER()
7674 if (Mask.getOpcode() == ISD::SETCC) { in visitMSTORE()
7743 if (Mask.getOpcode() != ISD::SETCC) in visitMGATHER()
7819 if (Mask.getOpcode() == ISD::SETCC) { in visitMLOAD()
7956 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
7964 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
7967 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
8011 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
8042 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
8043 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
8081 } else if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
8102 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
8113 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
8148 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
8222 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
8245 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
8254 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
8294 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
8295 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
8315 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
8326 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
8330 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
8380 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
8388 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
8393 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in CombineZExtLogicopShiftLoad()
8394 N0.getOpcode() == ISD::XOR) || in CombineZExtLogicopShiftLoad()
8395 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
8396 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
8401 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
8402 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
8403 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
8418 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
8435 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
8441 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
8461 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
8475 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
8476 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
8572 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
8573 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
8576 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
8595 auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
8611 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
8614 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
8682 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitSIGN_EXTEND()
8683 N0.getOpcode() == ISD::XOR) && in visitSIGN_EXTEND()
8685 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
8686 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
8701 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
8728 if (N0.getOpcode() == ISD::SETCC) { in visitSIGN_EXTEND()
8816 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
8822 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
8852 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
8874 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
8918 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
8919 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
8920 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
8948 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitZERO_EXTEND()
8949 N0.getOpcode() == ISD::XOR) && in visitZERO_EXTEND()
8951 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
8952 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
8960 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
8979 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
9016 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
9059 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
9061 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
9065 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
9081 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
9102 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
9103 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
9104 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
9105 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
9109 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
9122 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
9127 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
9128 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
9129 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
9177 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
9192 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
9237 unsigned Opcode = N->getOpcode(); in visitAssertExt()
9243 if (N0.getOpcode() == Opcode && in visitAssertExt()
9247 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
9248 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
9271 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
9272 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
9298 unsigned Opc = N->getOpcode(); in ReduceLoadWidth()
9357 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in ReduceLoadWidth()
9390 if (Mask->getOpcode() == ISD::AND && in ReduceLoadWidth()
9409 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in ReduceLoadWidth()
9521 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
9530 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
9540 if ((N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
9541 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
9542 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) && in visitSIGN_EXTEND_INREG()
9552 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
9576 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
9625 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
9677 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
9688 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
9689 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
9690 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
9693 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitTRUNCATE()
9703 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
9716 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
9742 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
9755 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
9779 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
9780 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
9818 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
9840 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
9884 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
9907 if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) && in visitTRUNCATE()
9909 (!LegalOperations || TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitTRUNCATE()
9914 return DAG.getNode(N0.getOpcode(), SL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
9921 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
9923 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
9924 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
9925 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
9940 switch (N0.getOpcode()) { in visitTRUNCATE()
9953 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
9957 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
9967 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
9975 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
10029 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
10053 LogicOp0.getOpcode() == ISD::BITCAST && in foldBitcastedFPLogic()
10057 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
10079 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && in visitBITCAST()
10101 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
10149 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
10150 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
10162 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
10166 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
10181 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
10184 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
10200 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && in visitBITCAST()
10264 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
10273 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
10281 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
10484 if (N.getOpcode() != ISD::FMUL) in visitFADDForFMACombine()
10511 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10525 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10541 N0.getOpcode() == PreferredFusedOpcode && in visitFADDForFMACombine()
10542 N0.getOperand(2).getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
10554 N1->getOpcode() == PreferredFusedOpcode && in visitFADDForFMACombine()
10555 N1.getOperand(2).getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
10577 if (N0.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
10579 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10606 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10608 if (N00.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
10621 if (N1.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
10623 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10639 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10641 if (N10.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
10696 if (N.getOpcode() != ISD::FMUL) in visitFSUBForFMACombine()
10718 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
10731 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10747 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10767 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10769 if (N00.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
10790 if (N0.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
10792 if (N00.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10811 if (CanFuse && N0.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
10825 if (CanFuse && N1.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
10841 if (N0.getOpcode() == PreferredFusedOpcode) { in visitFSUBForFMACombine()
10843 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10866 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10868 if (N00.getOpcode() == PreferredFusedOpcode) { in visitFSUBForFMACombine()
10890 if (N1.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
10891 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
10916 if (N1.getOpcode() == ISD::FP_EXTEND && in visitFSUBForFMACombine()
10917 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) { in visitFSUBForFMACombine()
10955 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
10986 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
11009 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
11085 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
11111 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
11115 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
11126 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
11136 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
11148 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
11157 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
11169 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
11178 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
11188 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
11199 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
11266 && N1.getOpcode() == ISD::FADD) { in visitFSUB()
11332 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
11346 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
11379 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
11382 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
11390 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
11471 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
11480 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
11507 if (N0.getOpcode() == ISD::FNEG && in visitFMA()
11525 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { in visitFMA()
11566 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
11644 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
11648 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
11649 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11656 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
11657 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11664 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
11669 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11672 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
11748 if ((N1.getOpcode() == ISD::FP_EXTEND || in CanCombineFCOPYSIGN_EXTEND_ROUND()
11749 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
11788 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
11789 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
11793 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
11797 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
11898 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
11902 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
11933 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
11947 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
11948 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && in visitSINT_TO_FP()
11990 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
12013 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
12018 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
12019 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
12083 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
12087 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
12114 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { in visitFP_ROUND()
12150 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
12158 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
12164 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
12219 switch (N0.getOpcode()) { in visitFTRUNC()
12259 N0.getOpcode() == ISD::BITCAST && in visitFNEG()
12283 if (N0.getOpcode() == ISD::FMUL && in visitFNEG()
12319 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
12349 if (N0.getOpcode() == ISD::FABS) in visitFABS()
12354 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
12358 if (!TLI.isFAbsFree(VT) && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse()) { in visitFABS()
12396 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
12413 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
12414 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
12416 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
12418 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
12441 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
12444 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
12460 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
12467 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
12480 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
12488 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
12491 Op0.getOpcode() == ISD::XOR) { in rebuildSetCC()
12527 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
12558 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
12566 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
12616 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
12682 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
12683 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
12774 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
12775 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
12844 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) in CombineToPostIndexedLoadStore()
12873 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ in CombineToPostIndexedLoadStore()
12942 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
12945 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
13144 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant && in visitLOAD()
13498 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
13707 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
13715 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
13761 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
13763 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
13783 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
13832 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
13928 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
13952 Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
14117 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
14153 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
14249 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in MergeStoresOfConstantsOrVecElts()
14250 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in MergeStoresOfConstantsOrVecElts()
14359 bool IsExtractVecSrc = (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in getStoreMergeCandidates()
14360 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR); in getStoreMergeCandidates()
14418 if (Val.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
14419 Val.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
14492 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
14552 bool IsExtractVecSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in MergeConsecutiveStores()
14553 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR); in MergeConsecutiveStores()
15076 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
15161 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
15245 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
15291 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) in visitSTORE()
15311 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
15372 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
15379 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
15381 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
15397 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
15400 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
15407 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
15410 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
15449 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
15511 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
15538 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
15561 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
15695 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
15714 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
15721 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
15740 if (IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR && in visitEXTRACT_VECTOR_ELT()
15757 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
15769 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
15800 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
15818 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
15844 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
15857 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
15872 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
15907 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
15934 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
15988 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
15989 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
16039 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
16040 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
16091 if (!VecIn2 || !(VecIn1.getOpcode() == ISD::EXTRACT_SUBVECTOR) || in createBuildVecShuffle()
16092 !(VecIn2.getOpcode() == ISD::EXTRACT_SUBVECTOR) || in createBuildVecShuffle()
16195 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
16222 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
16223 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
16320 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
16497 if (Op.getOpcode() == ISD::ZERO_EXTEND && in convertBuildVecZextToZext()
16498 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
16569 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
16625 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
16628 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
16689 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
16766 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
16778 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
16810 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
16822 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
16834 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
16837 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
16877 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
16954 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
16999 LHS.getOpcode() == ISD::CONCAT_VECTORS && LHS.getNumOperands() == 2; in narrowExtractedVectorBinOp()
17001 RHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getNumOperands() == 2; in narrowExtractedVectorBinOp()
17079 if (V.getOpcode() == ISD::CONCAT_VECTORS && in visitEXTRACT_SUBVECTOR()
17092 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
17127 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
17284 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
17286 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
17392 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
17541 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
17626 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
17633 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
17682 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
17685 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
17700 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
17715 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
17766 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
17767 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in visitVECTOR_SHUFFLE()
17790 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) && in visitVECTOR_SHUFFLE()
17902 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in visitSCALAR_TO_VECTOR()
17959 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
17967 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
17968 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
17981 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
17998 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
18007 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
18021 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
18037 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
18058 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
18068 if (N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
18084 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
18096 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
18181 N->getOpcode(), SDLoc(LHS), LHS.getValueType(), Ops, N->getFlags())) in SimplifyVBinOp()
18197 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT, in SimplifyVBinOp()
18211 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); in SimplifySelect()
18222 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
18247 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
18254 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
18261 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
18281 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
18289 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
18314 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
18341 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
18585 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
18663 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) in SimplifySelectCC()
18667 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) in SimplifySelectCC()
18702 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
18703 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
18709 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
18710 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
19169 switch (Chain.getOpcode()) { in GatherAllAliases()