Lines Matching refs:IsAnd
428 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
3982 SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, in foldLogicOfSetCCs() argument
4014 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero; in foldLogicOfSetCCs()
4016 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
4018 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero; in foldLogicOfSetCCs()
4020 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
4033 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1; in foldLogicOfSetCCs()
4035 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
4037 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1; in foldLogicOfSetCCs()
4039 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
4054 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && in foldLogicOfSetCCs()
4071 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) { in foldLogicOfSetCCs()
4089 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger) in foldLogicOfSetCCs()