Lines Matching refs:OperIdx
230 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
231 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
240 bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() && in addPhysRegDataDeps()
271 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
285 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
287 MachineOperand &MO = MI->getOperand(OperIdx); in addPhysRegDeps()
315 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
327 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
331 addPhysRegDataDeps(SU, OperIdx); in addPhysRegDeps()
358 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
382 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { in addVRegDefDeps() argument
384 MachineOperand &MO = MI->getOperand(OperIdx); in addVRegDefDeps()
423 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use, in addVRegDefDeps()
467 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
491 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { in addVRegUseDeps() argument
493 const MachineOperand &MO = MI->getOperand(OperIdx); in addVRegUseDeps()
499 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU)); in addVRegUseDeps()