304       SUnit *DefSU = I->SU;  in addPhysRegDeps()  local
305       if (DefSU == &ExitSU)  in addPhysRegDeps()
307       if (DefSU != SU &&  in addPhysRegDeps()
309            !DefSU->getInstr()->registerDefIsDead(*Alias))) {  in addPhysRegDeps()
311           DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));  in addPhysRegDeps()
315             SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addPhysRegDeps()
316           DefSU->addPred(Dep);  in addPhysRegDeps()
457     SUnit *DefSU = V2SU.SU;  in addVRegDefDeps()  local
463     if (DefSU == SU)  in addVRegDefDeps()
467       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
468     DefSU->addPred(Dep);  in addVRegDefDeps()
478       CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));  in addVRegDefDeps()