Lines Matching refs:DstInt
1325 LiveInterval &DstInt = LIS->getInterval(DstReg); in reMaterializeTrivialDef() local
1326 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1353 if (NewIdx == 0 && DstInt.hasSubRanges()) { in reMaterializeTrivialDef()
1359 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1365 LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask); in reMaterializeTrivialDef()
1378 if (NewIdx != 0 && DstInt.hasSubRanges()) { in reMaterializeTrivialDef()
1383 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1396 DstInt.removeEmptySubRanges(); in reMaterializeTrivialDef()
1624 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg); in updateRegDefsUses() local
1626 if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) { in updateRegDefsUses()
1635 addUndefFlag(*DstInt, UseIdx, MO, SubReg); in updateRegDefsUses()
1659 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue()) in updateRegDefsUses()
1660 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI)); in updateRegDefsUses()
1675 if (!DstInt->hasSubRanges()) { in updateRegDefsUses()
1677 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(DstInt->reg); in updateRegDefsUses()
1678 DstInt->createSubRangeFrom(Allocator, Mask, *DstInt); in updateRegDefsUses()
1684 addUndefFlag(*DstInt, UseIdx, MO, SubIdx); in updateRegDefsUses()