249     unsigned Cascade = 0;  member
883   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in canEvictInterference()  local
884   if (!Cascade)  in canEvictInterference()
885     Cascade = NextCascade;  in canEvictInterference()
913       unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;  in canEvictInterference()
914       if (Cascade <= IntfCascade) {  in canEvictInterference()
1041   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in evictInterference()  local
1042   if (!Cascade)  in evictInterference()
1043     Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;  in evictInterference()
1046                     << " interference: Cascade " << Cascade << '\n');  in evictInterference()
1071     assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||  in evictInterference()
1074     ExtraRegInfo[Intf->reg].Cascade = Cascade;  in evictInterference()
3045                     << ExtraRegInfo[VirtReg.reg].Cascade << '\n');  in selectOrSplitImpl()