Lines Matching refs:Def
255 RegSubRegPair Def, RewriteMapTy &RewriteMap);
367 const MachineInstr *Def = nullptr; member in __anon649c77ce0111::ValueTracker
423 Def = MRI.getVRegDef(Reg); in ValueTracker()
1113 RegSubRegPair Def, in getNewSource() argument
1116 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1224 RegSubRegPair Def, RewriteMapTy &RewriteMap) { in rewriteSource() argument
1225 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) && in rewriteSource()
1229 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1240 if (Def.SubReg) { in rewriteSource()
1241 NewCopy->getOperand(0).setSubReg(Def.SubReg); in rewriteSource()
1248 MRI->replaceRegWith(Def.Reg, NewVReg); in rewriteSource()
1279 RegSubRegPair Def; in optimizeUncoalescableCopy() local
1281 while (CpyRewriter.getNextRewritableSource(Src, Def)) { in optimizeUncoalescableCopy()
1284 if (TargetRegisterInfo::isPhysicalRegister(Def.Reg)) in optimizeUncoalescableCopy()
1289 if (!findNextSource(Def, RewriteMap)) in optimizeUncoalescableCopy()
1292 RewritePairs.push_back(Def); in optimizeUncoalescableCopy()
1296 for (const RegSubRegPair &Def : RewritePairs) { in optimizeUncoalescableCopy() local
1298 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap); in optimizeUncoalescableCopy()
1668 const auto &Def = NAPhysToVirtMIs.find(Reg); in runOnMachineFunction() local
1669 if (Def != NAPhysToVirtMIs.end()) { in runOnMachineFunction()
1674 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1680 unsigned Def = RegMI.first; in runOnMachineFunction() local
1681 if (MachineOperand::clobbersPhysReg(RegMask, Def)) { in runOnMachineFunction()
1684 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1809 assert(Def->isCopy() && "Invalid definition"); in getNextSourceFromCopy()
1812 assert(Def->getNumOperands() == 2 && "Invalid number of operands"); in getNextSourceFromCopy()
1814 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1819 const MachineOperand &Src = Def->getOperand(1); in getNextSourceFromCopy()
1826 assert(Def->isBitcast() && "Invalid definition"); in getNextSourceFromBitcast()
1829 if (Def->hasUnmodeledSideEffects()) in getNextSourceFromBitcast()
1833 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1835 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1841 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast()
1844 const MachineOperand &MO = Def->getOperand(OpIdx); in getNextSourceFromBitcast()
1864 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
1871 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1874 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1897 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1920 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
1923 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1936 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1952 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
1973 assert((Def->isExtractSubreg() || in getNextSourceFromExtractSubreg()
1974 Def->isExtractSubregLike()) && "Invalid definition"); in getNextSourceFromExtractSubreg()
1989 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg)) in getNextSourceFromExtractSubreg()
2002 assert(Def->isSubregToReg() && "Invalid definition"); in getNextSourceFromSubregToReg()
2010 if (DefSubReg != Def->getOperand(3).getImm()) in getNextSourceFromSubregToReg()
2014 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
2017 return ValueTrackerResult(Def->getOperand(2).getReg(), in getNextSourceFromSubregToReg()
2018 Def->getOperand(3).getImm()); in getNextSourceFromSubregToReg()
2023 assert(Def->isPHI() && "Invalid definition"); in getNextSourceFromPHI()
2028 if (Def->getOperand(0).getSubReg() != DefSubReg) in getNextSourceFromPHI()
2032 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { in getNextSourceFromPHI()
2033 const MachineOperand &MO = Def->getOperand(i); in getNextSourceFromPHI()
2046 assert(Def && "This method needs a valid definition"); in getNextSourceImpl()
2048 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2049 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2050 Def->getDesc().isVariadic())) || in getNextSourceImpl()
2051 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
2053 if (Def->isCopy()) in getNextSourceImpl()
2055 if (Def->isBitcast()) in getNextSourceImpl()
2061 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
2063 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
2065 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) in getNextSourceImpl()
2067 if (Def->isSubregToReg()) in getNextSourceImpl()
2069 if (Def->isPHI()) in getNextSourceImpl()
2077 if (!Def) in getNextSource()
2090 Res.setInst(Def); in getNextSource()
2097 Def = DI->getParent(); in getNextSource()
2101 Def = nullptr; in getNextSource()
2109 Def = nullptr; in getNextSource()