Lines Matching refs:addDef
323 auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1); in translateBinaryOp()
337 .addDef(getOrCreateVReg(U)) in translateFSub()
346 .addDef(getOrCreateVReg(U)) in translateFNeg()
641 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op); in translateCast()
763 MIB.addDef(DstReg); in getStackGuard()
783 .addDef(ResRegs[0]) in translateOverflowIntrinsic()
784 .addDef(ResRegs[1]) in translateOverflowIntrinsic()
894 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
902 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
909 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
916 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
923 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
930 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
937 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
944 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
949 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
954 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
1036 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
1042 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
1056 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
1379 .addDef(getOrCreateVReg(U)) in translateVAArg()
1449 .addDef(getOrCreateVReg(U)) in translateShuffleVector()