Lines Matching refs:OpNum
92 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
173 unsigned OpNum = MI.getOperandNo(&MO); in isCrossCopy() local
174 DstSubIdx = MI.getOperand(OpNum+1).getImm(); in isCrossCopy()
233 unsigned OpNum = MI.getOperandNo(&MO); in transferUsedLanes() local
242 assert(OpNum % 2 == 1); in transferUsedLanes()
243 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes()
250 if (OpNum == 2) in transferUsedLanes()
262 assert(OpNum == 1); in transferUsedLanes()
266 assert(OpNum == 1); in transferUsedLanes()
296 unsigned OpNum = MI.getOperandNo(&Use); in transferDefinedLanesStep() local
299 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
312 unsigned OpNum, LaneBitmask DefinedLanes) const { in transferDefinedLanes() argument
317 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes()
324 if (OpNum == 2) { in transferDefinedLanes()
328 assert(OpNum == 1 && "INSERT_SUBREG must have two operands"); in transferDefinedLanes()
336 assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only"); in transferDefinedLanes()
405 unsigned OpNum = DefMI.getOperandNo(&MO); in determineInitialDefinedLanes() local
406 DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes); in determineInitialDefinedLanes()