Lines Matching refs:Add
34 * i386.h: Add entries from config/tc-i386.h and move tables
44 * spu-insns.h: Add soma double-float insns.
49 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
50 (INSN_DSPR2): Add flag for DSP R2 instructions.
84 * score-inst.h (enum score_insn_type): Add Insn_internal.
129 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
133 * i386.h (i386_optab): Add "nop" with memory reference.
156 * mips.h (enum): Add macro M_CACHE_AB.
162 * mips.h: Add INSN_SMARTMIPS define.
167 * mips.h: Defines udi bits and masks. Add description of
211 * arm.h: Add V7 feature bits.
215 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
235 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
285 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
286 Add FLAG_STRICT to pa10 ftest opcode.
295 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
296 before corresponding pa11 opcodes. Add strict pa10 register-immediate
301 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
333 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
343 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
344 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
345 Add movq-s as 64-bit variants of movd-s.
351 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
353 using implicit space-register addressing. Add various missing pa20
372 * i386.h (i386_optab): Add new insns.
376 * sparc.h: Add typedefs to structure declarations.
413 * i386.h (i386_optab): Add ht and hnt.
418 Add xcrypt-ctr. Provide aliases without hyphens.
429 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
450 (instruction type): Add NO_TYPE_INS.
451 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
458 Add new unsigned immediate types us3, us4, us5, us16.
467 * i386.h (i386_optab): Add rdtscp.
478 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
488 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
493 * cgen.h (enum cgen_parse_operand_type): Add
504 * mips.h (struct mips_opcode): Add new pinfo2 member.
519 to/from test registers are illegal in 64-bit mode. Add missing
523 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
550 comments. Remove member cris_ver_sim. Add members
573 changes to the *FP macros. Add DefaultSize to floating point control
580 * crx.h: Add COPS_REG_INS - Coprocessor Special register
590 * avr.h: Add support for
599 * msp430.h (msp430_opc): Add new instructions.
641 * m68k.h: Add 'size' to m68k_opcode.
649 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
673 * h8300.h (32bit ldc/stc): Add relaxing support.