313 	uint32_t	val, val_temp;  in mv_delay()  local
316 	val = mv_get_timer(1);  in mv_delay()
321 		if (val > val_temp)  in mv_delay()
322 			nticks -= (val - val_temp);  in mv_delay()
324 			nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));  in mv_delay()
326 		val = val_temp;  in mv_delay()
334 	uint32_t	val;  in DELAY()  local
338 			for (val = 100; val > 0; val--)  in DELAY()
357 mv_set_timer_control(uint32_t val)  in mv_set_timer_control()  argument
361 	    timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);  in mv_set_timer_control()
373 mv_set_timer(uint32_t timer, uint32_t val)  in mv_set_timer()  argument
377 	    timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);  in mv_set_timer()
381 mv_set_timer_rel(uint32_t timer, uint32_t val)  in mv_set_timer_rel()  argument
385 	    timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);  in mv_set_timer_rel()
391 	uint32_t val, irq_cause, irq_mask;  in mv_watchdog_enable_armv5()  local
401 	val = read_cpu_ctrl(RSTOUTn_MASK);  in mv_watchdog_enable_armv5()
402 	val |= WD_RST_OUT_EN;  in mv_watchdog_enable_armv5()
403 	write_cpu_ctrl(RSTOUTn_MASK, val);  in mv_watchdog_enable_armv5()
405 	val = mv_get_timer_control();  in mv_watchdog_enable_armv5()
406 	val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;  in mv_watchdog_enable_armv5()
407 	mv_set_timer_control(val);  in mv_watchdog_enable_armv5()
413 	uint32_t irq_cause, val;  in mv_watchdog_enable_armadaxp()  local
419 	val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);  in mv_watchdog_enable_armadaxp()
420 	val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);  in mv_watchdog_enable_armadaxp()
421 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);  in mv_watchdog_enable_armadaxp()
423 	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);  in mv_watchdog_enable_armadaxp()
424 	val &= ~RSTOUTn_MASK_WD;  in mv_watchdog_enable_armadaxp()
425 	write_cpu_misc(RSTOUTn_MASK_ARMV7, val);  in mv_watchdog_enable_armadaxp()
427 	val = mv_get_timer_control();  in mv_watchdog_enable_armadaxp()
428 	val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;  in mv_watchdog_enable_armadaxp()
429 	mv_set_timer_control(val);  in mv_watchdog_enable_armadaxp()
435 	uint32_t val, irq_cause,irq_mask;  in mv_watchdog_disable_armv5()  local
437 	val = mv_get_timer_control();  in mv_watchdog_disable_armv5()
438 	val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);  in mv_watchdog_disable_armv5()
439 	mv_set_timer_control(val);  in mv_watchdog_disable_armv5()
441 	val = read_cpu_ctrl(RSTOUTn_MASK);  in mv_watchdog_disable_armv5()
442 	val &= ~WD_RST_OUT_EN;  in mv_watchdog_disable_armv5()
443 	write_cpu_ctrl(RSTOUTn_MASK, val);  in mv_watchdog_disable_armv5()
457 	uint32_t val, irq_cause;  in mv_watchdog_disable_armadaxp()  local
459 	val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);  in mv_watchdog_disable_armadaxp()
460 	val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);  in mv_watchdog_disable_armadaxp()
461 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);  in mv_watchdog_disable_armadaxp()
463 	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);  in mv_watchdog_disable_armadaxp()
464 	val |= RSTOUTn_MASK_WD;  in mv_watchdog_disable_armadaxp()
471 	val = mv_get_timer_control();  in mv_watchdog_disable_armadaxp()
472 	val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);  in mv_watchdog_disable_armadaxp()
473 	mv_set_timer_control(val);  in mv_watchdog_disable_armadaxp()
513 	uint32_t val, val1;  in mv_timer_start()  local
518 		val = ((uint32_t)sc->et.et_frequency * period) >> 32;  in mv_timer_start()
520 		val = 0;  in mv_timer_start()
524 		val1 = val;  in mv_timer_start()
527 	mv_set_timer_rel(0, val);  in mv_timer_start()
529 	val = mv_get_timer_control();  in mv_timer_start()
530 	val |= CPU_TIMER0_EN;  in mv_timer_start()
532 		val |= CPU_TIMER0_AUTO;  in mv_timer_start()
534 		val &= ~CPU_TIMER0_AUTO;  in mv_timer_start()
535 	mv_set_timer_control(val);  in mv_timer_start()
542 	uint32_t val;  in mv_timer_stop()  local
544 	val = mv_get_timer_control();  in mv_timer_stop()
545 	val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);  in mv_timer_stop()
546 	mv_set_timer_control(val);  in mv_timer_stop()
553 	uint32_t val;  in mv_setup_timers()  local
557 	val = mv_get_timer_control();  in mv_setup_timers()
558 	val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);  in mv_setup_timers()
559 	val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;  in mv_setup_timers()
563 		val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;  in mv_setup_timers()
566 	mv_set_timer_control(val);  in mv_setup_timers()