106 static struct mv_timer_softc *timer_softc = NULL;  variable
190 	if (timer_softc != NULL)  in mv_timer_attach()
194 	timer_softc = sc;  in mv_timer_attach()
213 	mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);  in mv_timer_attach()
276 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_hardclock()
277 	irq_cause &= timer_softc->config->irq_timer0_clr;  in mv_hardclock()
278 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_hardclock()
317 	nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);  in mv_delay()
352 	return (bus_space_read_4(timer_softc->timer_bst,  in mv_get_timer_control()
353 	    timer_softc->timer_bsh, CPU_TIMER_CONTROL));  in mv_get_timer_control()
360 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer_control()
361 	    timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);  in mv_set_timer_control()
368 	return (bus_space_read_4(timer_softc->timer_bst,  in mv_get_timer()
369 	    timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));  in mv_get_timer()
376 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer()
377 	    timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);  in mv_set_timer()
384 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer_rel()
385 	    timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);  in mv_set_timer_rel()
393 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_enable_armv5()
394 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_enable_armv5()
395 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_enable_armv5()
415 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_enable_armadaxp()
416 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_enable_armadaxp()
417 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_enable_armadaxp()
449 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_disable_armv5()
450 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_disable_armv5()
451 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_disable_armv5()
467 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_disable_armadaxp()
468 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_disable_armadaxp()
469 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_disable_armadaxp()
485 	mtx_lock(&timer_softc->timer_mtx);  in mv_watchdog_event()
487 		if (timer_softc->config->watchdog_disable != NULL)  in mv_watchdog_event()
488 			timer_softc->config->watchdog_disable();  in mv_watchdog_event()
495 		ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;  in mv_watchdog_event()
497 			if (timer_softc->config->watchdog_disable != NULL)  in mv_watchdog_event()
498 				timer_softc->config->watchdog_disable();  in mv_watchdog_event()
501 			if (timer_softc->config->watchdog_enable != NULL)  in mv_watchdog_event()
502 				timer_softc->config->watchdog_enable();  in mv_watchdog_event()
506 	mtx_unlock(&timer_softc->timer_mtx);  in mv_watchdog_event()
561 	if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {  in mv_setup_timers()