41 	struct pci_dev *pdev;  member
63 	struct pci_dev *pdev = to_pci_dev(dev);  in store_max_vfs()  local
69 		pci_disable_sriov(pdev);  in store_max_vfs()
70 	else if (0 == pci_num_vf(pdev))  in store_max_vfs()
71 		err = pci_enable_sriov(pdev, max_vfs);  in store_max_vfs()
116 igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)  in igbuio_msi_mask_irq()  argument
119 	u32 offset = desc->irq - pdev->irq;  in igbuio_msi_mask_irq()
131 		pci_write_config_dword(pdev, desc->mask_pos, mask_bits);  in igbuio_msi_mask_irq()
137 igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)  in igbuio_mask_irq()  argument
143 	msi_list = &pdev->dev.msi_list;  in igbuio_mask_irq()
145 	msi_list = &pdev->msi_list;  in igbuio_mask_irq()
153 			igbuio_msi_mask_irq(pdev, desc, irq_state);  in igbuio_mask_irq()
175 	struct pci_dev *pdev = udev->pdev;  in igbuio_pci_irqcontrol()  local
181 	pci_cfg_access_lock(pdev);  in igbuio_pci_irqcontrol()
190 		igbuio_mask_irq(pdev, udev->mode, irq_state);  in igbuio_pci_irqcontrol()
195 		pci_intx(pdev, !!irq_state);  in igbuio_pci_irqcontrol()
197 	pci_cfg_access_unlock(pdev);  in igbuio_pci_irqcontrol()
214 	    !pci_check_and_mask_intx(udev->pdev))  in igbuio_pci_irqhandler()
236 		if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {  in igbuio_pci_enable_interrupts()
237 			dev_dbg(&udev->pdev->dev, "using MSI-X");  in igbuio_pci_enable_interrupts()
244 		if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {  in igbuio_pci_enable_interrupts()
245 			dev_dbg(&udev->pdev->dev, "using MSI-X");  in igbuio_pci_enable_interrupts()
247 			udev->info.irq = pci_irq_vector(udev->pdev, 0);  in igbuio_pci_enable_interrupts()
256 		if (pci_enable_msi(udev->pdev) == 0) {  in igbuio_pci_enable_interrupts()
257 			dev_dbg(&udev->pdev->dev, "using MSI");  in igbuio_pci_enable_interrupts()
259 			udev->info.irq = udev->pdev->irq;  in igbuio_pci_enable_interrupts()
264 		if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {  in igbuio_pci_enable_interrupts()
265 			dev_dbg(&udev->pdev->dev, "using MSI");  in igbuio_pci_enable_interrupts()
267 			udev->info.irq = pci_irq_vector(udev->pdev, 0);  in igbuio_pci_enable_interrupts()
274 		if (pci_intx_mask_supported(udev->pdev)) {  in igbuio_pci_enable_interrupts()
275 			dev_dbg(&udev->pdev->dev, "using INTX");  in igbuio_pci_enable_interrupts()
277 			udev->info.irq = udev->pdev->irq;  in igbuio_pci_enable_interrupts()
281 		dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");  in igbuio_pci_enable_interrupts()
289 		dev_err(&udev->pdev->dev, "invalid IRQ mode %u",  in igbuio_pci_enable_interrupts()
299 	dev_info(&udev->pdev->dev, "uio device registered with irq %ld\n",  in igbuio_pci_enable_interrupts()
315 		pci_disable_msix(udev->pdev);  in igbuio_pci_disable_interrupts()
317 		pci_disable_msi(udev->pdev);  in igbuio_pci_disable_interrupts()
321 		pci_free_irq_vectors(udev->pdev);  in igbuio_pci_disable_interrupts()
333 	struct pci_dev *dev = udev->pdev;  in igbuio_pci_open()
355 	struct pci_dev *dev = udev->pdev;  in igbuio_pci_release()
534 	udev->pdev = dev;  in igbuio_pci_probe()