183 #define FWDSTEP	4  macro
703 	switch (n % FWDSTEP) {  in send_packetsx4()
733 		switch (len % FWDSTEP) {  in send_packetsx4()
1412 processx4_step1(struct rte_mbuf *pkt[FWDSTEP],  in processx4_step1()  argument
1451 		struct rte_mbuf *pkt[FWDSTEP],  in processx4_step2()  argument
1452 		uint16_t dprt[FWDSTEP])  in processx4_step2()  argument
1483 processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP])  in processx4_step3()  argument
1485 	__m128i te[FWDSTEP];  in processx4_step3()
1486 	__m128i ve[FWDSTEP];  in processx4_step3()
1487 	__m128i *p[FWDSTEP];  in processx4_step3()
1542 #define	GRPSZ	(1 << FWDSTEP)
1564 port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, __m128i dp1, __m128i dp2)  in port_groupx4()
1670 		uint16_t u16[FWDSTEP + 1];  in port_groupx4()
1686 		pnum->u16[FWDSTEP] = 1;  in port_groupx4()
1708 	__m128i dip[MAX_PKT_BURST / FWDSTEP];  in process_burst()
1709 	uint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP];  in process_burst()
1754 	k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);  in process_burst()
1755 	for (j = 0; j != k; j += FWDSTEP)  in process_burst()
1756 		processx4_step1(&pkts_burst[j], &dip[j / FWDSTEP],  in process_burst()
1757 				&ipv4_flag[j / FWDSTEP]);  in process_burst()
1759 	k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);  in process_burst()
1760 	for (j = 0; j != k; j += FWDSTEP)  in process_burst()
1761 		processx4_step2(dip[j / FWDSTEP], ipv4_flag[j / FWDSTEP],  in process_burst()
1768 	k = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);  in process_burst()
1780 		for (j = FWDSTEP; j != k; j += FWDSTEP) {  in process_burst()
1788 					(__m128i *)&dst_port[j - FWDSTEP + 1]);  in process_burst()
1789 			lp  = port_groupx4(&pnum[j - FWDSTEP], lp, dp1, dp2);  in process_burst()
1795 			dp1 = _mm_srli_si128(dp2, (FWDSTEP - 1) *  in process_burst()
1803 		lp  = port_groupx4(&pnum[j - FWDSTEP], lp, dp1, dp2);  in process_burst()
1818 	switch (nb_rx % FWDSTEP) {  in process_burst()