Lines Matching refs:base
116 gemac_enable_rx_checksum_offload(__rte_unused void *base) in gemac_enable_rx_checksum_offload() argument
126 gemac_disable_rx_checksum_offload(__rte_unused void *base) in gemac_disable_rx_checksum_offload() argument
136 gemac_set_speed(void *base, enum mac_speed gem_speed) in gemac_set_speed() argument
138 u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; in gemac_set_speed()
139 u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; in gemac_set_speed()
155 writel(ecr, (base + EMAC_ECNTRL_REG)); in gemac_set_speed()
156 writel(rcr, (base + EMAC_RCNTRL_REG)); in gemac_set_speed()
164 gemac_set_duplex(void *base, int duplex) in gemac_set_duplex() argument
167 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base in gemac_set_duplex()
169 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base in gemac_set_duplex()
172 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base in gemac_set_duplex()
174 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base in gemac_set_duplex()
184 gemac_set_mode(void *base, __rte_unused int mode) in gemac_set_mode() argument
186 u32 val = readl(base + EMAC_RCNTRL_REG); in gemac_set_mode()
194 writel(val, base + EMAC_RCNTRL_REG); in gemac_set_mode()
201 gemac_enable(void *base) in gemac_enable() argument
203 writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + in gemac_enable()
211 gemac_disable(void *base) in gemac_disable() argument
213 writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + in gemac_disable()
221 gemac_tx_disable(void *base) in gemac_tx_disable() argument
223 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + in gemac_tx_disable()
228 gemac_tx_enable(void *base) in gemac_tx_enable() argument
230 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + in gemac_tx_enable()
241 gemac_set_hash(void *base, struct pfe_mac_addr *hash) in gemac_set_hash() argument
243 writel(hash->bottom, base + EMAC_GALR); in gemac_set_hash()
244 writel(hash->top, base + EMAC_GAUR); in gemac_set_hash()
248 gemac_set_laddrN(void *base, struct pfe_mac_addr *address, in gemac_set_laddrN() argument
256 writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); in gemac_set_laddrN()
257 writel((htonl(address->top) | 0x8808), base + in gemac_set_laddrN()
260 writel(htonl(address->bottom), base + ((entry_index - 1) * 8) in gemac_set_laddrN()
262 writel((htonl(address->top) | 0x8808), base + ((entry_index - in gemac_set_laddrN()
268 gemac_clear_laddrN(void *base, unsigned int entry_index) in gemac_clear_laddrN() argument
275 writel(0, base + EMAC_PHY_ADDR_LOW); in gemac_clear_laddrN()
276 writel(0, base + EMAC_PHY_ADDR_HIGH); in gemac_clear_laddrN()
278 writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); in gemac_clear_laddrN()
279 writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); in gemac_clear_laddrN()
294 gemac_set_loop(void *base, __rte_unused enum mac_loop gem_loop) in gemac_set_loop() argument
297 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + in gemac_set_loop()
305 gemac_enable_copy_all(void *base) in gemac_enable_copy_all() argument
307 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + in gemac_enable_copy_all()
315 gemac_disable_copy_all(void *base) in gemac_disable_copy_all() argument
317 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + in gemac_disable_copy_all()
325 gemac_allow_broadcast(void *base) in gemac_allow_broadcast() argument
327 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + in gemac_allow_broadcast()
335 gemac_no_broadcast(void *base) in gemac_no_broadcast() argument
337 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + in gemac_no_broadcast()
345 gemac_enable_1536_rx(void *base) in gemac_enable_1536_rx() argument
348 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) in gemac_enable_1536_rx()
350 base + EMAC_RCNTRL_REG); in gemac_enable_1536_rx()
357 gemac_set_rx(void *base, int mtu) in gemac_set_rx() argument
370 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) in gemac_set_rx()
372 base + EMAC_RCNTRL_REG); in gemac_set_rx()
380 gemac_enable_rx_jmb(void *base) in gemac_enable_rx_jmb() argument
387 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) | in gemac_enable_rx_jmb()
388 (JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG); in gemac_enable_rx_jmb()
395 gemac_enable_stacked_vlan(__rte_unused void *base) in gemac_enable_stacked_vlan() argument
404 gemac_enable_pause_rx(void *base) in gemac_enable_pause_rx() argument
406 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, in gemac_enable_pause_rx()
407 base + EMAC_RCNTRL_REG); in gemac_enable_pause_rx()
414 gemac_disable_pause_rx(void *base) in gemac_disable_pause_rx() argument
416 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, in gemac_disable_pause_rx()
417 base + EMAC_RCNTRL_REG); in gemac_disable_pause_rx()
424 gemac_enable_pause_tx(void *base) in gemac_enable_pause_tx() argument
426 writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY); in gemac_enable_pause_tx()
433 gemac_disable_pause_tx(void *base) in gemac_disable_pause_tx() argument
435 writel(0x0, base + EMAC_RX_SECTION_EMPTY); in gemac_disable_pause_tx()
443 gemac_set_wol(void *base, u32 wol_conf) in gemac_set_wol() argument
445 u32 val = readl(base + EMAC_ECNTRL_REG); in gemac_set_wol()
451 writel(val, base + EMAC_ECNTRL_REG); in gemac_set_wol()
459 gemac_set_bus_width(__rte_unused void *base, __rte_unused int width) in gemac_set_bus_width() argument
468 gemac_set_config(void *base, struct gemac_cfg *cfg) in gemac_set_config() argument
471 writel(0x00000004, base + EMAC_TFWR_STR_FWD); in gemac_set_config()
472 writel(0x00000005, base + EMAC_RX_SECTION_FULL); in gemac_set_config()
475 writel(0x00000768, base + EMAC_TRUNC_FL); in gemac_set_config()
477 writel(0x00003fff, base + EMAC_TRUNC_FL); in gemac_set_config()
479 writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); in gemac_set_config()
480 writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); in gemac_set_config()
482 gemac_set_mode(base, cfg->mode); in gemac_set_config()
484 gemac_set_speed(base, cfg->speed); in gemac_set_config()
486 gemac_set_duplex(base, cfg->duplex); in gemac_set_config()
496 gpi_init(void *base, struct gpi_cfg *cfg) in gpi_init() argument
498 gpi_reset(base); in gpi_init()
500 gpi_disable(base); in gpi_init()
502 gpi_set_config(base, cfg); in gpi_init()
509 gpi_reset(void *base) in gpi_reset() argument
511 writel(CORE_SW_RESET, base + GPI_CTRL); in gpi_reset()
518 gpi_enable(void *base) in gpi_enable() argument
520 writel(CORE_ENABLE, base + GPI_CTRL); in gpi_enable()
527 gpi_disable(void *base) in gpi_disable() argument
529 writel(CORE_DISABLE, base + GPI_CTRL); in gpi_disable()
537 gpi_set_config(void *base, struct gpi_cfg *cfg) in gpi_set_config() argument
539 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base in gpi_set_config()
541 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base in gpi_set_config()
543 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base in gpi_set_config()
545 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base in gpi_set_config()
547 writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); in gpi_set_config()
548 writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); in gpi_set_config()
549 writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); in gpi_set_config()
550 writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); in gpi_set_config()
551 writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); in gpi_set_config()
552 writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); in gpi_set_config()
553 writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); in gpi_set_config()
556 GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); in gpi_set_config()
557 writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); in gpi_set_config()
558 writel(cfg->aseq_len, base + GPI_DTX_ASEQ); in gpi_set_config()
559 writel(1, base + GPI_TOE_CHKSUM_EN); in gpi_set_config()
562 writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); in gpi_set_config()
563 writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); in gpi_set_config()