4802 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)  in ixgbe_dcb_pfc_enable_generic()  argument
4820 		if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {  in ixgbe_dcb_pfc_enable_generic()
4826 		if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {  in ixgbe_dcb_pfc_enable_generic()
4905 		hw->fc.high_water[tc_num]) {  in ixgbe_dcb_pfc_enable_generic()
4906 		fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_dcb_pfc_enable_generic()
4907 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);  in ixgbe_dcb_pfc_enable_generic()
4908 		fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_dcb_pfc_enable_generic()
4910 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);  in ixgbe_dcb_pfc_enable_generic()
4917 		fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;  in ixgbe_dcb_pfc_enable_generic()
4919 	IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);  in ixgbe_dcb_pfc_enable_generic()
4934 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)  in ixgbe_dcb_pfc_enable()  argument
4940 		ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);  in ixgbe_dcb_pfc_enable()
4951 	uint8_t tc_num;  in ixgbe_priority_flow_ctrl_set()  local
4968 	tc_num = map[pfc_conf->priority];  in ixgbe_priority_flow_ctrl_set()
4969 	rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));  in ixgbe_priority_flow_ctrl_set()
4987 	hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;  in ixgbe_priority_flow_ctrl_set()
4988 	hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;  in ixgbe_priority_flow_ctrl_set()
4990 	err = ixgbe_dcb_pfc_enable(dev, tc_num);  in ixgbe_priority_flow_ctrl_set()