286 		uint8_t rule_id, uint8_t on);
288 		uint8_t	rule_id);
5738 		      uint8_t rule_id, uint8_t on)  in ixgbe_mirror_rule_set()  argument
5764 	if (rule_id >= IXGBE_MAX_MIRROR_RULES)  in ixgbe_mirror_rule_set()
5804 			mr_info->mr_conf[rule_id].vlan.vlan_mask =  in ixgbe_mirror_rule_set()
5808 					mr_info->mr_conf[rule_id].vlan.vlan_id[i] =  in ixgbe_mirror_rule_set()
5814 			mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;  in ixgbe_mirror_rule_set()
5816 				mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;  in ixgbe_mirror_rule_set()
5829 			mr_info->mr_conf[rule_id].pool_mask =  in ixgbe_mirror_rule_set()
5835 			mr_info->mr_conf[rule_id].pool_mask = 0;  in ixgbe_mirror_rule_set()
5844 	mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));  in ixgbe_mirror_rule_set()
5854 	mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;  in ixgbe_mirror_rule_set()
5855 	mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;  in ixgbe_mirror_rule_set()
5858 	IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);  in ixgbe_mirror_rule_set()
5862 		IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);  in ixgbe_mirror_rule_set()
5863 		IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),  in ixgbe_mirror_rule_set()
5868 		IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);  in ixgbe_mirror_rule_set()
5869 		IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),  in ixgbe_mirror_rule_set()
5877 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)  in ixgbe_mirror_rule_reset()  argument
5892 	if (rule_id >= IXGBE_MAX_MIRROR_RULES)  in ixgbe_mirror_rule_reset()
5895 	memset(&mr_info->mr_conf[rule_id], 0,  in ixgbe_mirror_rule_reset()
5899 	IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);  in ixgbe_mirror_rule_reset()
5902 	IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);  in ixgbe_mirror_rule_reset()
5903 	IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);  in ixgbe_mirror_rule_reset()
5906 	IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);  in ixgbe_mirror_rule_reset()
5907 	IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);  in ixgbe_mirror_rule_reset()