2469 		for (i = 0; i < pf->vf_num; i++) {  in i40e_dev_start()
3466 		for (i = 0; i < pf->vf_num; i++) {  in i40e_dev_stats_get()
4827 		pf->vf_num = pci_dev->max_vfs;  in i40e_pf_parameter_init()
4830 			pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);  in i40e_pf_parameter_init()
4833 		pf->vf_num = 0;  in i40e_pf_parameter_init()
4835 	qp_count += pf->vf_nb_qps * pf->vf_num;  in i40e_pf_parameter_init()
4836 	vsi_count += pf->vf_num;  in i40e_pf_parameter_init()
4839 	pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;  in i40e_pf_parameter_init()
5814 		ctxt.vf_num = 0;  in i40e_vsi_setup()
5850 		ctxt.vf_num = 0;  in i40e_vsi_setup()
5893 		ctxt.vf_num = hw->func_caps.vf_base_id + user_param;  in i40e_vsi_setup()
5936 		ctxt.vf_num = 0;  in i40e_vsi_setup()
5969 		ctxt.vf_num = 0;  in i40e_vsi_setup()
6673 	for (i = 0; i < pf->vf_num; i++) {  in i40e_dev_handle_vfr_event()
6703 	for (i = 0; i < pf->vf_num; i++)  in i40e_notify_all_vfs_link_status()
6776 		uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>  in i40e_handle_mdd_event()  local
6785 				event, queue, pf_num, vf_num, dev->data->name);  in i40e_handle_mdd_event()
6821 	for (i = 0; i < pf->vf_num && mdd_detected; i++) {  in i40e_handle_mdd_event()
8558 		if (tunnel_filter->vf_id >= pf->vf_num) {  in i40e_dev_consistent_tunnel_filter_set()
10346 	if (mirror_conf->dst_pool > pf->vf_num) {  in i40e_mirror_rule_set()
10411 		if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {  in i40e_mirror_rule_set()
10416 		for (i = 0, j = 0; i < pf->vf_num; i++) {  in i40e_mirror_rule_set()
10422 		if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {  in i40e_mirror_rule_set()
10453 	if (mirror_conf->dst_pool == pf->vf_num)  in i40e_mirror_rule_set()
11039 	ctxt.vf_num = 0;  in i40e_vsi_config_tc()
11301 	if (pf->vf_num != 0)  in i40e_dcb_setup()