Lines Matching refs:ena_dev
68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, in ena_com_mem_addr_set() argument
72 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { in ena_com_mem_addr_set()
309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, in ena_com_init_io_sq() argument
318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits; in ena_com_init_io_sq()
325 io_sq->bus = ena_dev->bus; in ena_com_init_io_sq()
328 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, in ena_com_init_io_sq()
336 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_init_io_sq()
352 ena_dev->llq_info.desc_list_entry_size; in ena_com_init_io_sq()
360 ENA_MEM_ALLOC_NODE(ena_dev->dmadev, in ena_com_init_io_sq()
366 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size); in ena_com_init_io_sq()
373 memcpy(&io_sq->llq_info, &ena_dev->llq_info, in ena_com_init_io_sq()
398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, in ena_com_init_io_cq() argument
414 io_cq->bus = ena_dev->bus; in ena_com_init_io_cq()
416 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(ena_dev->dmadev, in ena_com_init_io_cq()
425 ENA_MEM_ALLOC_COHERENT_ALIGNED(ena_dev->dmadev, in ena_com_init_io_cq()
569 admin_queue->ena_dev->ena_min_poll_delay_us); in ena_com_wait_and_process_admin_cq_polling()
596 static int ena_com_set_llq(struct ena_com_dev *ena_dev) in ena_com_set_llq() argument
601 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; in ena_com_set_llq()
605 admin_queue = &ena_dev->admin_queue; in ena_com_set_llq()
631 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, in ena_com_config_llq_info() argument
635 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; in ena_com_config_llq_info()
751 rc = ena_com_set_llq(ena_dev); in ena_com_config_llq_info()
809 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) in ena_com_reg_bar_read32() argument
811 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_reg_bar_read32()
825 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset); in ena_com_reg_bar_read32()
836 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, in ena_com_reg_bar_read32()
837 ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); in ena_com_reg_bar_read32()
886 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, in ena_com_destroy_io_sq() argument
889 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_destroy_io_sq()
921 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, in ena_com_io_queue_free() argument
930 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_io_queue_free()
942 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_io_queue_free()
952 ENA_MEM_FREE(ena_dev->dmadev, in ena_com_io_queue_free()
959 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, in wait_for_reset_state() argument
969 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in wait_for_reset_state()
983 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); in wait_for_reset_state()
987 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, in ena_com_check_supported_feature_id() argument
994 !(ena_dev->supported_features & feature_mask)) in ena_com_check_supported_feature_id()
1000 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, in ena_com_get_feature_ex() argument
1011 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { in ena_com_get_feature_ex()
1017 admin_queue = &ena_dev->admin_queue; in ena_com_get_feature_ex()
1027 ret = ena_com_mem_addr_set(ena_dev, in ena_com_get_feature_ex()
1054 static int ena_com_get_feature(struct ena_com_dev *ena_dev, in ena_com_get_feature() argument
1059 return ena_com_get_feature_ex(ena_dev, in ena_com_get_feature()
1067 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev) in ena_com_get_current_hash_function() argument
1069 return ena_dev->rss.hash_func; in ena_com_get_current_hash_function()
1072 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) in ena_com_hash_key_fill_default_key() argument
1075 (ena_dev->rss).hash_key; in ena_com_hash_key_fill_default_key()
1084 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) in ena_com_hash_key_allocate() argument
1086 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_key_allocate()
1088 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) in ena_com_hash_key_allocate()
1091 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_hash_key_allocate()
1103 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) in ena_com_hash_key_destroy() argument
1105 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_key_destroy()
1108 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_hash_key_destroy()
1116 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) in ena_com_hash_ctrl_init() argument
1118 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_ctrl_init()
1120 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_hash_ctrl_init()
1132 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) in ena_com_hash_ctrl_destroy() argument
1134 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_ctrl_destroy()
1137 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_hash_ctrl_destroy()
1145 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, in ena_com_indirect_table_allocate() argument
1148 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_allocate()
1153 ret = ena_com_get_feature(ena_dev, &get_resp, in ena_com_indirect_table_allocate()
1170 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_indirect_table_allocate()
1180 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size); in ena_com_indirect_table_allocate()
1192 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_indirect_table_allocate()
1203 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) in ena_com_indirect_table_destroy() argument
1205 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_destroy()
1210 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_indirect_table_destroy()
1218 ENA_MEM_FREE(ena_dev->dmadev, in ena_com_indirect_table_destroy()
1224 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, in ena_com_create_io_sq() argument
1227 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_create_io_sq()
1260 ret = ena_com_mem_addr_set(ena_dev, in ena_com_create_io_sq()
1281 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_sq()
1285 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar in ena_com_create_io_sq()
1289 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + in ena_com_create_io_sq()
1298 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) in ena_com_ind_tbl_convert_to_device() argument
1300 struct ena_rss *rss = &ena_dev->rss; in ena_com_ind_tbl_convert_to_device()
1310 io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_ind_tbl_convert_to_device()
1321 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, in ena_com_update_intr_delay_resolution() argument
1324 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; in ena_com_update_intr_delay_resolution()
1332 ena_dev->intr_moder_rx_interval = in ena_com_update_intr_delay_resolution()
1333 ena_dev->intr_moder_rx_interval * in ena_com_update_intr_delay_resolution()
1338 ena_dev->intr_moder_tx_interval = in ena_com_update_intr_delay_resolution()
1339 ena_dev->intr_moder_tx_interval * in ena_com_update_intr_delay_resolution()
1343 ena_dev->intr_delay_resolution = intr_delay_resolution; in ena_com_update_intr_delay_resolution()
1384 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, in ena_com_create_io_cq() argument
1387 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_create_io_cq()
1404 ret = ena_com_mem_addr_set(ena_dev, in ena_com_create_io_cq()
1424 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1429 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1434 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1442 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, in ena_com_get_io_handlers() argument
1452 *io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_get_io_handlers()
1453 *io_cq = &ena_dev->io_cq_queues[qid]; in ena_com_get_io_handlers()
1458 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) in ena_com_abort_admin_commands() argument
1460 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_abort_admin_commands()
1478 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) in ena_com_wait_for_abort_completion() argument
1480 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_wait_for_abort_completion()
1487 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); in ena_com_wait_for_abort_completion()
1493 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, in ena_com_destroy_io_cq() argument
1496 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_destroy_io_cq()
1518 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) in ena_com_get_admin_running_state() argument
1520 return ena_dev->admin_queue.running_state; in ena_com_get_admin_running_state()
1523 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) in ena_com_set_admin_running_state() argument
1525 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_admin_running_state()
1529 ena_dev->admin_queue.running_state = state; in ena_com_set_admin_running_state()
1533 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) in ena_com_admin_aenq_enable() argument
1535 u16 depth = ena_dev->aenq.q_depth; in ena_com_admin_aenq_enable()
1537 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); in ena_com_admin_aenq_enable()
1542 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); in ena_com_admin_aenq_enable()
1545 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) in ena_com_set_aenq_config() argument
1553 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); in ena_com_set_aenq_config()
1567 admin_queue = &ena_dev->admin_queue; in ena_com_set_aenq_config()
1586 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) in ena_com_get_dma_width() argument
1588 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); in ena_com_get_dma_width()
1606 ena_dev->dma_addr_bits = width; in ena_com_get_dma_width()
1611 int ena_com_validate_version(struct ena_com_dev *ena_dev) in ena_com_validate_version() argument
1620 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); in ena_com_validate_version()
1621 ctrl_ver = ena_com_reg_bar_read32(ena_dev, in ena_com_validate_version()
1658 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) in ena_com_admin_destroy() argument
1660 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_admin_destroy()
1663 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_destroy()
1668 ENA_MEM_FREE(ena_dev->dmadev, in ena_com_admin_destroy()
1676 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, in ena_com_admin_destroy()
1682 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries, in ena_com_admin_destroy()
1687 if (ena_dev->aenq.entries) in ena_com_admin_destroy()
1688 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries, in ena_com_admin_destroy()
1694 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) in ena_com_set_admin_polling_mode() argument
1701 ENA_REG_WRITE32(ena_dev->bus, mask_value, in ena_com_set_admin_polling_mode()
1702 ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); in ena_com_set_admin_polling_mode()
1703 ena_dev->admin_queue.polling = polling; in ena_com_set_admin_polling_mode()
1706 bool ena_com_get_admin_polling_mode(struct ena_com_dev *ena_dev) in ena_com_get_admin_polling_mode() argument
1708 return ena_dev->admin_queue.polling; in ena_com_get_admin_polling_mode()
1711 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, in ena_com_set_admin_auto_polling_mode() argument
1714 ena_dev->admin_queue.auto_polling = polling; in ena_com_set_admin_auto_polling_mode()
1717 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_init() argument
1719 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_init()
1722 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_mmio_reg_read_request_init()
1730 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); in ena_com_mmio_reg_read_request_init()
1743 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) in ena_com_set_mmio_read_mode() argument
1745 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_set_mmio_read_mode()
1750 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_destroy() argument
1752 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_destroy()
1754 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); in ena_com_mmio_reg_read_request_destroy()
1755 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); in ena_com_mmio_reg_read_request_destroy()
1757 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_mmio_reg_read_request_destroy()
1767 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_write_dev_addr() argument
1769 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_write_dev_addr()
1775 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); in ena_com_mmio_reg_read_request_write_dev_addr()
1776 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); in ena_com_mmio_reg_read_request_write_dev_addr()
1779 int ena_com_admin_init(struct ena_com_dev *ena_dev, in ena_com_admin_init() argument
1782 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_admin_init()
1786 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in ena_com_admin_init()
1800 admin_queue->bus = ena_dev->bus; in ena_com_admin_init()
1801 admin_queue->q_dmadev = ena_dev->dmadev; in ena_com_admin_init()
1821 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_admin_init()
1827 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); in ena_com_admin_init()
1828 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); in ena_com_admin_init()
1833 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); in ena_com_admin_init()
1834 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); in ena_com_admin_init()
1848 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); in ena_com_admin_init()
1849 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); in ena_com_admin_init()
1850 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); in ena_com_admin_init()
1854 admin_queue->ena_dev = ena_dev; in ena_com_admin_init()
1859 ena_com_admin_destroy(ena_dev); in ena_com_admin_init()
1864 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, in ena_com_create_io_queue() argument
1877 io_sq = &ena_dev->io_sq_queues[ctx->qid]; in ena_com_create_io_queue()
1878 io_cq = &ena_dev->io_cq_queues[ctx->qid]; in ena_com_create_io_queue()
1899 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256); in ena_com_create_io_queue()
1901 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); in ena_com_create_io_queue()
1904 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); in ena_com_create_io_queue()
1908 ret = ena_com_create_io_cq(ena_dev, io_cq); in ena_com_create_io_queue()
1912 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); in ena_com_create_io_queue()
1919 ena_com_destroy_io_cq(ena_dev, io_cq); in ena_com_create_io_queue()
1921 ena_com_io_queue_free(ena_dev, io_sq, io_cq); in ena_com_create_io_queue()
1925 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) in ena_com_destroy_io_queue() argument
1936 io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_destroy_io_queue()
1937 io_cq = &ena_dev->io_cq_queues[qid]; in ena_com_destroy_io_queue()
1939 ena_com_destroy_io_sq(ena_dev, io_sq); in ena_com_destroy_io_queue()
1940 ena_com_destroy_io_cq(ena_dev, io_cq); in ena_com_destroy_io_queue()
1942 ena_com_io_queue_free(ena_dev, io_sq, io_cq); in ena_com_destroy_io_queue()
1945 int ena_com_get_link_params(struct ena_com_dev *ena_dev, in ena_com_get_link_params() argument
1948 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); in ena_com_get_link_params()
1951 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, in ena_com_get_dev_attr_feat() argument
1957 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1964 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; in ena_com_get_dev_attr_feat()
1966 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { in ena_com_get_dev_attr_feat()
1967 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1978 ena_dev->tx_max_header_size = in ena_com_get_dev_attr_feat()
1981 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1985 ena_dev->tx_max_header_size = in ena_com_get_dev_attr_feat()
1992 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
2000 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
2011 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0); in ena_com_get_dev_attr_feat()
2021 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0); in ena_com_get_dev_attr_feat()
2030 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
2044 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) in ena_com_admin_q_comp_intr_handler() argument
2046 ena_com_handle_admin_completion(&ena_dev->admin_queue); in ena_com_admin_q_comp_intr_handler()
2129 int ena_com_dev_reset(struct ena_com_dev *ena_dev, in ena_com_dev_reset() argument
2135 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in ena_com_dev_reset()
2136 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); in ena_com_dev_reset()
2160 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); in ena_com_dev_reset()
2163 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); in ena_com_dev_reset()
2165 rc = wait_for_reset_state(ena_dev, timeout, in ena_com_dev_reset()
2173 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); in ena_com_dev_reset()
2174 rc = wait_for_reset_state(ena_dev, timeout, 0); in ena_com_dev_reset()
2184 ena_dev->admin_queue.completion_timeout = timeout * 100000; in ena_com_dev_reset()
2186 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; in ena_com_dev_reset()
2191 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, in ena_get_dev_stats() argument
2200 admin_queue = &ena_dev->admin_queue; in ena_get_dev_stats()
2218 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, in ena_com_get_eni_stats() argument
2225 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI); in ena_com_get_eni_stats()
2233 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, in ena_com_get_dev_basic_stats() argument
2240 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); in ena_com_get_dev_basic_stats()
2248 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) in ena_com_set_dev_mtu() argument
2255 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { in ena_com_set_dev_mtu()
2261 admin_queue = &ena_dev->admin_queue; in ena_com_set_dev_mtu()
2280 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, in ena_com_get_offload_settings() argument
2286 ret = ena_com_get_feature(ena_dev, &resp, in ena_com_get_offload_settings()
2298 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) in ena_com_set_hash_function() argument
2300 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_hash_function()
2301 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_hash_function()
2307 if (!ena_com_check_supported_feature_id(ena_dev, in ena_com_set_hash_function()
2315 ret = ena_com_get_feature(ena_dev, &get_resp, in ena_com_set_hash_function()
2335 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_hash_function()
2359 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, in ena_com_fill_hash_function() argument
2366 struct ena_rss *rss = &ena_dev->rss; in ena_com_fill_hash_function()
2375 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_fill_hash_function()
2410 rc = ena_com_set_hash_function(ena_dev); in ena_com_fill_hash_function()
2419 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, in ena_com_get_hash_function() argument
2422 struct ena_rss *rss = &ena_dev->rss; in ena_com_get_hash_function()
2429 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_get_hash_function()
2446 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) in ena_com_get_hash_key() argument
2449 ena_dev->rss.hash_key; in ena_com_get_hash_key()
2457 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, in ena_com_get_hash_ctrl() argument
2461 struct ena_rss *rss = &ena_dev->rss; in ena_com_get_hash_ctrl()
2465 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_get_hash_ctrl()
2478 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) in ena_com_set_hash_ctrl() argument
2480 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_hash_ctrl()
2481 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_hash_ctrl()
2487 if (!ena_com_check_supported_feature_id(ena_dev, in ena_com_set_hash_ctrl()
2504 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_hash_ctrl()
2524 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) in ena_com_set_default_hash_ctrl() argument
2526 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_default_hash_ctrl()
2533 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_set_default_hash_ctrl()
2576 rc = ena_com_set_hash_ctrl(ena_dev); in ena_com_set_default_hash_ctrl()
2580 ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_set_default_hash_ctrl()
2585 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, in ena_com_fill_hash_ctrl() argument
2589 struct ena_rss *rss = &ena_dev->rss; in ena_com_fill_hash_ctrl()
2600 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); in ena_com_fill_hash_ctrl()
2613 rc = ena_com_set_hash_ctrl(ena_dev); in ena_com_fill_hash_ctrl()
2617 ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_fill_hash_ctrl()
2622 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, in ena_com_indirect_table_fill_entry() argument
2625 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_fill_entry()
2638 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) in ena_com_indirect_table_set() argument
2640 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_indirect_table_set()
2641 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_set()
2646 if (!ena_com_check_supported_feature_id(ena_dev, in ena_com_indirect_table_set()
2653 ret = ena_com_ind_tbl_convert_to_device(ena_dev); in ena_com_indirect_table_set()
2668 ret = ena_com_mem_addr_set(ena_dev, in ena_com_indirect_table_set()
2691 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) in ena_com_indirect_table_get() argument
2693 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_get()
2701 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_indirect_table_get()
2717 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) in ena_com_rss_init() argument
2721 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); in ena_com_rss_init()
2723 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); in ena_com_rss_init()
2731 rc = ena_com_hash_key_allocate(ena_dev); in ena_com_rss_init()
2733 ena_com_hash_key_fill_default_key(ena_dev); in ena_com_rss_init()
2737 rc = ena_com_hash_ctrl_init(ena_dev); in ena_com_rss_init()
2744 ena_com_hash_key_destroy(ena_dev); in ena_com_rss_init()
2746 ena_com_indirect_table_destroy(ena_dev); in ena_com_rss_init()
2752 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) in ena_com_rss_destroy() argument
2754 ena_com_indirect_table_destroy(ena_dev); in ena_com_rss_destroy()
2755 ena_com_hash_key_destroy(ena_dev); in ena_com_rss_destroy()
2756 ena_com_hash_ctrl_destroy(ena_dev); in ena_com_rss_destroy()
2758 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); in ena_com_rss_destroy()
2761 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) in ena_com_allocate_host_info() argument
2763 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_allocate_host_info()
2765 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_allocate_host_info()
2780 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, in ena_com_allocate_debug_area() argument
2783 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_allocate_debug_area()
2785 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, in ena_com_allocate_debug_area()
2800 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) in ena_com_delete_host_info() argument
2802 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_delete_host_info()
2805 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_delete_host_info()
2814 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) in ena_com_delete_debug_area() argument
2816 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_delete_debug_area()
2819 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, in ena_com_delete_debug_area()
2828 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) in ena_com_set_host_attributes() argument
2830 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_set_host_attributes()
2842 admin_queue = &ena_dev->admin_queue; in ena_com_set_host_attributes()
2847 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_host_attributes()
2855 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_host_attributes()
2878 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) in ena_com_interrupt_moderation_supported() argument
2880 return ena_com_check_supported_feature_id(ena_dev, in ena_com_interrupt_moderation_supported()
2899 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, in ena_com_update_nonadaptive_moderation_interval_tx() argument
2903 ena_dev->intr_delay_resolution, in ena_com_update_nonadaptive_moderation_interval_tx()
2904 &ena_dev->intr_moder_tx_interval); in ena_com_update_nonadaptive_moderation_interval_tx()
2907 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, in ena_com_update_nonadaptive_moderation_interval_rx() argument
2911 ena_dev->intr_delay_resolution, in ena_com_update_nonadaptive_moderation_interval_rx()
2912 &ena_dev->intr_moder_rx_interval); in ena_com_update_nonadaptive_moderation_interval_rx()
2915 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) in ena_com_init_interrupt_moderation() argument
2921 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_init_interrupt_moderation()
2935 ena_com_disable_adaptive_moderation(ena_dev); in ena_com_init_interrupt_moderation()
2941 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); in ena_com_init_interrupt_moderation()
2944 ena_com_disable_adaptive_moderation(ena_dev); in ena_com_init_interrupt_moderation()
2949 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) in ena_com_get_nonadaptive_moderation_interval_tx() argument
2951 return ena_dev->intr_moder_tx_interval; in ena_com_get_nonadaptive_moderation_interval_tx()
2954 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) in ena_com_get_nonadaptive_moderation_interval_rx() argument
2956 return ena_dev->intr_moder_rx_interval; in ena_com_get_nonadaptive_moderation_interval_rx()
2959 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, in ena_com_config_dev_mode() argument
2963 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; in ena_com_config_dev_mode()
2967 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; in ena_com_config_dev_mode()
2971 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); in ena_com_config_dev_mode()
2975 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - in ena_com_config_dev_mode()
2978 if (unlikely(ena_dev->tx_max_header_size == 0)) { in ena_com_config_dev_mode()
2983 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; in ena_com_config_dev_mode()