Lines Matching refs:pdata
11 static inline unsigned int axgbe_get_max_frame(struct axgbe_port *pdata) in axgbe_get_max_frame() argument
13 return pdata->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + in axgbe_get_max_frame()
18 static int mdio_complete(struct axgbe_port *pdata) in mdio_complete() argument
20 if (!AXGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, BUSY)) in mdio_complete()
26 static int axgbe_write_ext_mii_regs(struct axgbe_port *pdata, int addr, in axgbe_write_ext_mii_regs() argument
35 AXGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in axgbe_write_ext_mii_regs()
41 AXGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in axgbe_write_ext_mii_regs()
46 if (mdio_complete(pdata)) in axgbe_write_ext_mii_regs()
54 static int axgbe_read_ext_mii_regs(struct axgbe_port *pdata, int addr, in axgbe_read_ext_mii_regs() argument
63 AXGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in axgbe_read_ext_mii_regs()
68 AXGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in axgbe_read_ext_mii_regs()
74 if (mdio_complete(pdata)) in axgbe_read_ext_mii_regs()
82 return AXGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); in axgbe_read_ext_mii_regs()
85 static int axgbe_set_ext_mii_mode(struct axgbe_port *pdata, unsigned int port, in axgbe_set_ext_mii_mode() argument
101 AXGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in axgbe_set_ext_mii_mode()
106 static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata, in axgbe_read_mmd_regs_v2() argument
115 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in axgbe_read_mmd_regs_v2()
127 index = mmd_address & ~pdata->xpcs_window_mask; in axgbe_read_mmd_regs_v2()
128 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in axgbe_read_mmd_regs_v2()
130 pthread_mutex_lock(&pdata->xpcs_mutex); in axgbe_read_mmd_regs_v2()
132 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in axgbe_read_mmd_regs_v2()
133 mmd_data = XPCS16_IOREAD(pdata, offset); in axgbe_read_mmd_regs_v2()
135 pthread_mutex_unlock(&pdata->xpcs_mutex); in axgbe_read_mmd_regs_v2()
140 static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata, in axgbe_write_mmd_regs_v2() argument
149 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in axgbe_write_mmd_regs_v2()
161 index = mmd_address & ~pdata->xpcs_window_mask; in axgbe_write_mmd_regs_v2()
162 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in axgbe_write_mmd_regs_v2()
164 pthread_mutex_lock(&pdata->xpcs_mutex); in axgbe_write_mmd_regs_v2()
166 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in axgbe_write_mmd_regs_v2()
167 XPCS16_IOWRITE(pdata, offset, mmd_data); in axgbe_write_mmd_regs_v2()
169 pthread_mutex_unlock(&pdata->xpcs_mutex); in axgbe_write_mmd_regs_v2()
172 static int axgbe_read_mmd_regs(struct axgbe_port *pdata, int prtad, in axgbe_read_mmd_regs() argument
175 switch (pdata->vdata->xpcs_access) { in axgbe_read_mmd_regs()
181 return axgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); in axgbe_read_mmd_regs()
185 static void axgbe_write_mmd_regs(struct axgbe_port *pdata, int prtad, in axgbe_write_mmd_regs() argument
188 switch (pdata->vdata->xpcs_access) { in axgbe_write_mmd_regs()
194 return axgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); in axgbe_write_mmd_regs()
198 static int axgbe_set_speed(struct axgbe_port *pdata, int speed) in axgbe_set_speed() argument
216 if (AXGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in axgbe_set_speed()
217 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in axgbe_set_speed()
222 static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata) in axgbe_disable_tx_flow_control() argument
229 for (i = 0; i < pdata->rx_q_count; i++) in axgbe_disable_tx_flow_control()
230 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in axgbe_disable_tx_flow_control()
234 q_count = RTE_MIN(pdata->tx_q_count, in axgbe_disable_tx_flow_control()
238 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_disable_tx_flow_control()
240 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_disable_tx_flow_control()
248 static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata) in axgbe_enable_tx_flow_control() argument
255 for (i = 0; i < pdata->rx_q_count; i++) { in axgbe_enable_tx_flow_control()
259 if (pdata->rx_rfd[i]) in axgbe_enable_tx_flow_control()
262 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in axgbe_enable_tx_flow_control()
270 q_count = RTE_MIN(pdata->tx_q_count, in axgbe_enable_tx_flow_control()
274 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_enable_tx_flow_control()
281 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_enable_tx_flow_control()
289 static int axgbe_disable_rx_flow_control(struct axgbe_port *pdata) in axgbe_disable_rx_flow_control() argument
291 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in axgbe_disable_rx_flow_control()
296 static int axgbe_enable_rx_flow_control(struct axgbe_port *pdata) in axgbe_enable_rx_flow_control() argument
298 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in axgbe_enable_rx_flow_control()
303 static int axgbe_config_tx_flow_control(struct axgbe_port *pdata) in axgbe_config_tx_flow_control() argument
305 if (pdata->tx_pause) in axgbe_config_tx_flow_control()
306 axgbe_enable_tx_flow_control(pdata); in axgbe_config_tx_flow_control()
308 axgbe_disable_tx_flow_control(pdata); in axgbe_config_tx_flow_control()
313 static int axgbe_config_rx_flow_control(struct axgbe_port *pdata) in axgbe_config_rx_flow_control() argument
315 if (pdata->rx_pause) in axgbe_config_rx_flow_control()
316 axgbe_enable_rx_flow_control(pdata); in axgbe_config_rx_flow_control()
318 axgbe_disable_rx_flow_control(pdata); in axgbe_config_rx_flow_control()
323 static void axgbe_config_flow_control(struct axgbe_port *pdata) in axgbe_config_flow_control() argument
325 axgbe_config_tx_flow_control(pdata); in axgbe_config_flow_control()
326 axgbe_config_rx_flow_control(pdata); in axgbe_config_flow_control()
328 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); in axgbe_config_flow_control()
331 static void axgbe_queue_flow_control_threshold(struct axgbe_port *pdata, in axgbe_queue_flow_control_threshold() argument
338 frame_fifo_size = AXGMAC_FLOW_CONTROL_ALIGN(axgbe_get_max_frame(pdata)); in axgbe_queue_flow_control_threshold()
347 pdata->rx_rfa[queue] = 0; in axgbe_queue_flow_control_threshold()
348 pdata->rx_rfd[queue] = 0; in axgbe_queue_flow_control_threshold()
354 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in axgbe_queue_flow_control_threshold()
355 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in axgbe_queue_flow_control_threshold()
361 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in axgbe_queue_flow_control_threshold()
362 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in axgbe_queue_flow_control_threshold()
382 pdata->rx_rfa[queue] = AXGMAC_FLOW_CONTROL_VALUE(rfa); in axgbe_queue_flow_control_threshold()
383 pdata->rx_rfd[queue] = AXGMAC_FLOW_CONTROL_VALUE(rfd); in axgbe_queue_flow_control_threshold()
386 static void axgbe_calculate_flow_control_threshold(struct axgbe_port *pdata) in axgbe_calculate_flow_control_threshold() argument
391 for (i = 0; i < pdata->rx_q_count; i++) { in axgbe_calculate_flow_control_threshold()
392 q_fifo_size = (pdata->fifo + 1) * AXGMAC_FIFO_UNIT; in axgbe_calculate_flow_control_threshold()
394 axgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in axgbe_calculate_flow_control_threshold()
398 static void axgbe_config_flow_control_threshold(struct axgbe_port *pdata) in axgbe_config_flow_control_threshold() argument
402 for (i = 0; i < pdata->rx_q_count; i++) { in axgbe_config_flow_control_threshold()
403 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in axgbe_config_flow_control_threshold()
404 pdata->rx_rfa[i]); in axgbe_config_flow_control_threshold()
405 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in axgbe_config_flow_control_threshold()
406 pdata->rx_rfd[i]); in axgbe_config_flow_control_threshold()
410 static int __axgbe_exit(struct axgbe_port *pdata) in __axgbe_exit() argument
415 AXGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __axgbe_exit()
419 while (--count && AXGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __axgbe_exit()
428 static int axgbe_exit(struct axgbe_port *pdata) in axgbe_exit() argument
435 ret = __axgbe_exit(pdata); in axgbe_exit()
439 return __axgbe_exit(pdata); in axgbe_exit()
442 static int axgbe_flush_tx_queues(struct axgbe_port *pdata) in axgbe_flush_tx_queues() argument
446 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in axgbe_flush_tx_queues()
449 for (i = 0; i < pdata->tx_q_count; i++) in axgbe_flush_tx_queues()
450 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in axgbe_flush_tx_queues()
453 for (i = 0; i < pdata->tx_q_count; i++) { in axgbe_flush_tx_queues()
455 while (--count && AXGMAC_MTL_IOREAD_BITS(pdata, i, in axgbe_flush_tx_queues()
466 static void axgbe_config_dma_bus(struct axgbe_port *pdata) in axgbe_config_dma_bus() argument
469 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); in axgbe_config_dma_bus()
472 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, RD_OSR, 0x3f); in axgbe_config_dma_bus()
473 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, WR_OSR, 0x3f); in axgbe_config_dma_bus()
476 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); in axgbe_config_dma_bus()
477 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_32, 1); in axgbe_config_dma_bus()
478 AXGMAC_IOWRITE_BITS(pdata, DMA_SBMR, AAL, 1); in axgbe_config_dma_bus()
481 static void axgbe_config_dma_cache(struct axgbe_port *pdata) in axgbe_config_dma_cache() argument
487 AXGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); in axgbe_config_dma_cache()
497 AXGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); in axgbe_config_dma_cache()
503 AXGMAC_IOWRITE(pdata, DMA_AXIAWRCR, arwcache); in axgbe_config_dma_cache()
506 static void axgbe_config_edma_control(struct axgbe_port *pdata) in axgbe_config_edma_control() argument
508 AXGMAC_IOWRITE(pdata, EDMA_TX_CONTROL, 0x5); in axgbe_config_edma_control()
509 AXGMAC_IOWRITE(pdata, EDMA_RX_CONTROL, 0x5); in axgbe_config_edma_control()
512 static int axgbe_config_osp_mode(struct axgbe_port *pdata) in axgbe_config_osp_mode() argument
520 for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) { in axgbe_config_osp_mode()
521 txq = pdata->eth_dev->data->tx_queues[i]; in axgbe_config_osp_mode()
523 pdata->tx_osp_mode); in axgbe_config_osp_mode()
529 static int axgbe_config_pblx8(struct axgbe_port *pdata) in axgbe_config_pblx8() argument
534 for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) { in axgbe_config_pblx8()
535 txq = pdata->eth_dev->data->tx_queues[i]; in axgbe_config_pblx8()
537 pdata->pblx8); in axgbe_config_pblx8()
542 static int axgbe_config_tx_pbl_val(struct axgbe_port *pdata) in axgbe_config_tx_pbl_val() argument
547 for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) { in axgbe_config_tx_pbl_val()
548 txq = pdata->eth_dev->data->tx_queues[i]; in axgbe_config_tx_pbl_val()
550 pdata->tx_pbl); in axgbe_config_tx_pbl_val()
556 static int axgbe_config_rx_pbl_val(struct axgbe_port *pdata) in axgbe_config_rx_pbl_val() argument
561 for (i = 0; i < pdata->eth_dev->data->nb_rx_queues; i++) { in axgbe_config_rx_pbl_val()
562 rxq = pdata->eth_dev->data->rx_queues[i]; in axgbe_config_rx_pbl_val()
564 pdata->rx_pbl); in axgbe_config_rx_pbl_val()
570 static void axgbe_config_rx_buffer_size(struct axgbe_port *pdata) in axgbe_config_rx_buffer_size() argument
575 for (i = 0; i < pdata->eth_dev->data->nb_rx_queues; i++) { in axgbe_config_rx_buffer_size()
576 rxq = pdata->eth_dev->data->rx_queues[i]; in axgbe_config_rx_buffer_size()
583 if (rxq->buf_size > pdata->rx_buf_size) in axgbe_config_rx_buffer_size()
584 pdata->rx_buf_size = rxq->buf_size; in axgbe_config_rx_buffer_size()
591 static int axgbe_write_rss_reg(struct axgbe_port *pdata, unsigned int type, in axgbe_write_rss_reg() argument
596 if (AXGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in axgbe_write_rss_reg()
599 AXGMAC_IOWRITE(pdata, MAC_RSSDR, val); in axgbe_write_rss_reg()
601 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in axgbe_write_rss_reg()
602 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in axgbe_write_rss_reg()
603 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in axgbe_write_rss_reg()
604 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in axgbe_write_rss_reg()
608 if (!AXGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in axgbe_write_rss_reg()
617 int axgbe_write_rss_hash_key(struct axgbe_port *pdata) in axgbe_write_rss_hash_key() argument
620 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in axgbe_write_rss_hash_key()
624 rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf; in axgbe_write_rss_hash_key()
627 key = (unsigned int *)&pdata->rss_key; in axgbe_write_rss_hash_key()
632 ret = axgbe_write_rss_reg(pdata, AXGBE_RSS_HASH_KEY_TYPE, in axgbe_write_rss_hash_key()
641 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata) in axgbe_write_rss_lookup_table() argument
646 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in axgbe_write_rss_lookup_table()
647 ret = axgbe_write_rss_reg(pdata, in axgbe_write_rss_lookup_table()
649 pdata->rss_table[i]); in axgbe_write_rss_lookup_table()
657 static int axgbe_enable_rss(struct axgbe_port *pdata) in axgbe_enable_rss() argument
662 ret = axgbe_write_rss_hash_key(pdata); in axgbe_enable_rss()
667 ret = axgbe_write_rss_lookup_table(pdata); in axgbe_enable_rss()
672 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in axgbe_enable_rss()
675 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in axgbe_enable_rss()
680 static void axgbe_rss_options(struct axgbe_port *pdata) in axgbe_rss_options() argument
685 rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf; in axgbe_rss_options()
686 pdata->rss_hf = rss_conf->rss_hf; in axgbe_rss_options()
690 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); in axgbe_rss_options()
692 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); in axgbe_rss_options()
694 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); in axgbe_rss_options()
697 static int axgbe_config_rss(struct axgbe_port *pdata) in axgbe_config_rss() argument
701 if (pdata->rss_enable) { in axgbe_config_rss()
703 uint32_t *key = (uint32_t *)pdata->rss_key; in axgbe_config_rss()
705 for (i = 0; i < sizeof(pdata->rss_key) / 4; i++) in axgbe_config_rss()
708 AXGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, in axgbe_config_rss()
709 i % pdata->eth_dev->data->nb_rx_queues); in axgbe_config_rss()
710 axgbe_rss_options(pdata); in axgbe_config_rss()
711 if (axgbe_enable_rss(pdata)) { in axgbe_config_rss()
716 AXGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in axgbe_config_rss()
722 static void axgbe_enable_dma_interrupts(struct axgbe_port *pdata) in axgbe_enable_dma_interrupts() argument
728 for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) { in axgbe_enable_dma_interrupts()
729 txq = pdata->eth_dev->data->tx_queues[i]; in axgbe_enable_dma_interrupts()
759 static void wrapper_tx_desc_init(struct axgbe_port *pdata) in wrapper_tx_desc_init() argument
764 for (i = 0; i < pdata->eth_dev->data->nb_tx_queues; i++) { in wrapper_tx_desc_init()
765 txq = pdata->eth_dev->data->tx_queues[i]; in wrapper_tx_desc_init()
778 static int wrapper_rx_desc_init(struct axgbe_port *pdata) in wrapper_rx_desc_init() argument
785 for (i = 0; i < pdata->eth_dev->data->nb_rx_queues; i++) { in wrapper_rx_desc_init()
786 rxq = pdata->eth_dev->data->rx_queues[i]; in wrapper_rx_desc_init()
835 static void axgbe_config_mtl_mode(struct axgbe_port *pdata) in axgbe_config_mtl_mode() argument
840 AXGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in axgbe_config_mtl_mode()
843 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in axgbe_config_mtl_mode()
844 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in axgbe_config_mtl_mode()
846 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in axgbe_config_mtl_mode()
850 AXGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in axgbe_config_mtl_mode()
853 static int axgbe_config_tsf_mode(struct axgbe_port *pdata, unsigned int val) in axgbe_config_tsf_mode() argument
857 for (i = 0; i < pdata->tx_q_count; i++) in axgbe_config_tsf_mode()
858 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in axgbe_config_tsf_mode()
863 static int axgbe_config_rsf_mode(struct axgbe_port *pdata, unsigned int val) in axgbe_config_rsf_mode() argument
867 for (i = 0; i < pdata->rx_q_count; i++) in axgbe_config_rsf_mode()
868 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in axgbe_config_rsf_mode()
873 static int axgbe_config_tx_threshold(struct axgbe_port *pdata, in axgbe_config_tx_threshold() argument
878 for (i = 0; i < pdata->tx_q_count; i++) in axgbe_config_tx_threshold()
879 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in axgbe_config_tx_threshold()
884 static int axgbe_config_rx_threshold(struct axgbe_port *pdata, in axgbe_config_rx_threshold() argument
889 for (i = 0; i < pdata->rx_q_count; i++) in axgbe_config_rx_threshold()
890 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in axgbe_config_rx_threshold()
896 static void axgbe_config_rx_fifo_size(struct axgbe_port *pdata) in axgbe_config_rx_fifo_size() argument
902 fifo_size = RTE_MIN(pdata->rx_max_fifo_size, in axgbe_config_rx_fifo_size()
903 pdata->hw_feat.rx_fifo_size); in axgbe_config_rx_fifo_size()
904 q_fifo_size = fifo_size / pdata->rx_q_count; in axgbe_config_rx_fifo_size()
915 for (i = 0; i < pdata->rx_q_count; i++) in axgbe_config_rx_fifo_size()
916 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, p_fifo); in axgbe_config_rx_fifo_size()
917 pdata->fifo = p_fifo; in axgbe_config_rx_fifo_size()
920 axgbe_calculate_flow_control_threshold(pdata); in axgbe_config_rx_fifo_size()
921 axgbe_config_flow_control_threshold(pdata); in axgbe_config_rx_fifo_size()
924 pdata->rx_q_count, q_fifo_size); in axgbe_config_rx_fifo_size()
927 static void axgbe_config_tx_fifo_size(struct axgbe_port *pdata) in axgbe_config_tx_fifo_size() argument
933 fifo_size = RTE_MIN(pdata->tx_max_fifo_size, in axgbe_config_tx_fifo_size()
934 pdata->hw_feat.tx_fifo_size); in axgbe_config_tx_fifo_size()
935 q_fifo_size = fifo_size / pdata->tx_q_count; in axgbe_config_tx_fifo_size()
946 for (i = 0; i < pdata->tx_q_count; i++) in axgbe_config_tx_fifo_size()
947 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, p_fifo); in axgbe_config_tx_fifo_size()
950 pdata->tx_q_count, q_fifo_size); in axgbe_config_tx_fifo_size()
953 static void axgbe_config_queue_mapping(struct axgbe_port *pdata) in axgbe_config_queue_mapping() argument
961 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in axgbe_config_queue_mapping()
962 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in axgbe_config_queue_mapping()
964 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in axgbe_config_queue_mapping()
967 AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in axgbe_config_queue_mapping()
972 AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in axgbe_config_queue_mapping()
977 if (pdata->rss_enable) { in axgbe_config_queue_mapping()
981 for (i = 0; i < pdata->rx_q_count;) { in axgbe_config_queue_mapping()
985 (i != pdata->rx_q_count)) in axgbe_config_queue_mapping()
988 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_config_queue_mapping()
996 static void axgbe_enable_mtl_interrupts(struct axgbe_port *pdata) in axgbe_enable_mtl_interrupts() argument
1001 q_count = RTE_MAX(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in axgbe_enable_mtl_interrupts()
1004 mtl_q_isr = AXGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in axgbe_enable_mtl_interrupts()
1005 AXGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in axgbe_enable_mtl_interrupts()
1008 AXGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in axgbe_enable_mtl_interrupts()
1033 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add) in axgbe_set_mac_hash_table() argument
1038 crc >>= pdata->hash_table_shift; in axgbe_set_mac_hash_table()
1043 pdata->uc_hash_table[htable_index] |= htable_bitmask; in axgbe_set_mac_hash_table()
1044 pdata->uc_hash_mac_addr++; in axgbe_set_mac_hash_table()
1046 pdata->uc_hash_table[htable_index] &= ~htable_bitmask; in axgbe_set_mac_hash_table()
1047 pdata->uc_hash_mac_addr--; in axgbe_set_mac_hash_table()
1052 AXGMAC_IOWRITE(pdata, MAC_HTR(htable_index), in axgbe_set_mac_hash_table()
1053 pdata->uc_hash_table[htable_index]); in axgbe_set_mac_hash_table()
1056 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t index) in axgbe_set_mac_addn_addr() argument
1081 AXGMAC_IOWRITE(pdata, MAC_MACAHR(index), mac_addr_hi); in axgbe_set_mac_addn_addr()
1082 AXGMAC_IOWRITE(pdata, MAC_MACALR(index), mac_addr_lo); in axgbe_set_mac_addn_addr()
1085 static int axgbe_set_mac_address(struct axgbe_port *pdata, u8 *addr) in axgbe_set_mac_address() argument
1093 AXGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in axgbe_set_mac_address()
1094 AXGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in axgbe_set_mac_address()
1099 static void axgbe_config_mac_hash_table(struct axgbe_port *pdata) in axgbe_config_mac_hash_table() argument
1101 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; in axgbe_config_mac_hash_table()
1103 pdata->hash_table_shift = 0; in axgbe_config_mac_hash_table()
1104 pdata->hash_table_count = 0; in axgbe_config_mac_hash_table()
1105 pdata->uc_hash_mac_addr = 0; in axgbe_config_mac_hash_table()
1106 memset(pdata->uc_hash_table, 0, sizeof(pdata->uc_hash_table)); in axgbe_config_mac_hash_table()
1109 pdata->hash_table_shift = 26 - (hw_feat->hash_table_size >> 7); in axgbe_config_mac_hash_table()
1110 pdata->hash_table_count = hw_feat->hash_table_size / 32; in axgbe_config_mac_hash_table()
1114 static void axgbe_config_mac_address(struct axgbe_port *pdata) in axgbe_config_mac_address() argument
1116 axgbe_set_mac_address(pdata, pdata->mac_addr.addr_bytes); in axgbe_config_mac_address()
1119 static void axgbe_config_jumbo_enable(struct axgbe_port *pdata) in axgbe_config_jumbo_enable() argument
1123 val = (pdata->rx_buf_size > AXGMAC_STD_PACKET_MTU) ? 1 : 0; in axgbe_config_jumbo_enable()
1125 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in axgbe_config_jumbo_enable()
1128 static void axgbe_config_mac_speed(struct axgbe_port *pdata) in axgbe_config_mac_speed() argument
1130 axgbe_set_speed(pdata, pdata->phy_speed); in axgbe_config_mac_speed()
1133 static void axgbe_config_checksum_offload(struct axgbe_port *pdata) in axgbe_config_checksum_offload() argument
1135 if (pdata->rx_csum_enable) in axgbe_config_checksum_offload()
1136 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in axgbe_config_checksum_offload()
1138 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in axgbe_config_checksum_offload()
1141 static void axgbe_config_mmc(struct axgbe_port *pdata) in axgbe_config_mmc() argument
1143 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; in axgbe_config_mmc()
1149 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in axgbe_config_mmc()
1152 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in axgbe_config_mmc()
1155 static int axgbe_init(struct axgbe_port *pdata) in axgbe_init() argument
1160 ret = axgbe_flush_tx_queues(pdata); in axgbe_init()
1164 axgbe_config_dma_bus(pdata); in axgbe_init()
1165 axgbe_config_dma_cache(pdata); in axgbe_init()
1166 axgbe_config_edma_control(pdata); in axgbe_init()
1167 axgbe_config_osp_mode(pdata); in axgbe_init()
1168 axgbe_config_pblx8(pdata); in axgbe_init()
1169 axgbe_config_tx_pbl_val(pdata); in axgbe_init()
1170 axgbe_config_rx_pbl_val(pdata); in axgbe_init()
1171 axgbe_config_rx_buffer_size(pdata); in axgbe_init()
1172 axgbe_config_rss(pdata); in axgbe_init()
1173 wrapper_tx_desc_init(pdata); in axgbe_init()
1174 ret = wrapper_rx_desc_init(pdata); in axgbe_init()
1177 axgbe_enable_dma_interrupts(pdata); in axgbe_init()
1180 axgbe_config_mtl_mode(pdata); in axgbe_init()
1181 axgbe_config_queue_mapping(pdata); in axgbe_init()
1182 axgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in axgbe_init()
1183 axgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in axgbe_init()
1184 axgbe_config_tx_threshold(pdata, pdata->tx_threshold); in axgbe_init()
1185 axgbe_config_rx_threshold(pdata, pdata->rx_threshold); in axgbe_init()
1186 axgbe_config_tx_fifo_size(pdata); in axgbe_init()
1187 axgbe_config_rx_fifo_size(pdata); in axgbe_init()
1189 axgbe_enable_mtl_interrupts(pdata); in axgbe_init()
1192 axgbe_config_mac_hash_table(pdata); in axgbe_init()
1193 axgbe_config_mac_address(pdata); in axgbe_init()
1194 axgbe_config_jumbo_enable(pdata); in axgbe_init()
1195 axgbe_config_flow_control(pdata); in axgbe_init()
1196 axgbe_config_mac_speed(pdata); in axgbe_init()
1197 axgbe_config_checksum_offload(pdata); in axgbe_init()
1198 axgbe_config_mmc(pdata); in axgbe_init()