71 		void *vaddr = (void *)(dev->pci.mem_resource[2].addr);  in ccp_read_hwrng()  local
74 			*value = CCP_READ_REG(vaddr, TRNG_OUT_REG);  in ccp_read_hwrng()
490 	void *vaddr;  in ccp_add_device()  local
497 	vaddr = (void *)(dev->pci.mem_resource[2].addr);  in ccp_add_device()
500 		CCP_WRITE_REG(vaddr, CMD_TRNG_CTL_OFFSET, 0x00012D57);  in ccp_add_device()
501 		CCP_WRITE_REG(vaddr, CMD_CONFIG_0_OFFSET, 0x00000003);  in ccp_add_device()
503 			CCP_WRITE_REG(vaddr, CMD_AES_MASK_OFFSET,  in ccp_add_device()
504 				      CCP_READ_REG(vaddr, TRNG_OUT_REG));  in ccp_add_device()
506 		CCP_WRITE_REG(vaddr, CMD_QUEUE_MASK_OFFSET, 0x0000001F);  in ccp_add_device()
507 		CCP_WRITE_REG(vaddr, CMD_QUEUE_PRIO_OFFSET, 0x00005B6D);  in ccp_add_device()
508 		CCP_WRITE_REG(vaddr, CMD_CMD_TIMEOUT_OFFSET, 0x00000000);  in ccp_add_device()
510 		CCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET, 0x3FFFFFFF);  in ccp_add_device()
511 		CCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET, 0x000003FF);  in ccp_add_device()
513 		CCP_WRITE_REG(vaddr, CMD_CLK_GATE_CTL_OFFSET, 0x00108823);  in ccp_add_device()
515 	CCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x00001249);  in ccp_add_device()
518 	status_lo = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET);  in ccp_add_device()
519 	status_hi = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET);  in ccp_add_device()
520 	CCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_LO_OFFSET, status_lo);  in ccp_add_device()
521 	CCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_HI_OFFSET, status_hi);  in ccp_add_device()
526 	qmr = CCP_READ_REG(vaddr, Q_MASK_REG);  in ccp_add_device()
536 		cmd_q->reg_base = (uint8_t *)vaddr +  in ccp_add_device()