Lines Matching refs:uint32_t
27 uint32_t umem_id;
28 uint32_t pd;
29 uint32_t log_entity_size;
30 uint32_t pg_access:1;
31 uint32_t relaxed_ordering_write:1;
32 uint32_t relaxed_ordering_read:1;
39 uint32_t sup:1; /* Whether QOS is supported. */
40 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
41 uint32_t packet_pacing:1; /* Packet pacing is supported. */
42 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
43 uint32_t flow_meter_reg_share:1;
54 uint32_t valid:1;
55 uint32_t desc_tunnel_offload_type:1;
56 uint32_t eth_frame_offload_type:1;
57 uint32_t virtio_version_1_0:1;
58 uint32_t tso_ipv4:1;
59 uint32_t tso_ipv6:1;
60 uint32_t tx_csum:1;
61 uint32_t rx_csum:1;
62 uint32_t event_mode:3;
63 uint32_t log_doorbell_stride:5;
64 uint32_t log_doorbell_bar_size:5;
65 uint32_t queue_counters_valid:1;
66 uint32_t max_num_virtio_queues;
68 uint32_t a;
69 uint32_t b;
79 uint32_t eswitch_manager:1;
80 uint32_t flow_counters_dump:1;
81 uint32_t log_max_rqt_size:5;
82 uint32_t parse_graph_flex_node:1;
84 uint32_t eth_net_offloads:1;
85 uint32_t eth_virt:1;
86 uint32_t wqe_vlan_insert:1;
87 uint32_t wqe_inline_mode:2;
88 uint32_t vport_inline_mode:3;
89 uint32_t tunnel_stateless_geneve_rx:1;
90 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
91 uint32_t tunnel_stateless_gtp:1;
92 uint32_t lro_cap:1;
93 uint32_t tunnel_lro_gre:1;
94 uint32_t tunnel_lro_vxlan:1;
95 uint32_t lro_max_msg_sz_mode:2;
96 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
98 uint32_t flex_parser_protocols;
99 uint32_t hairpin:1;
100 uint32_t log_max_hairpin_queues:5;
101 uint32_t log_max_hairpin_wq_data_sz:5;
102 uint32_t log_max_hairpin_num_packets:5;
103 uint32_t vhca_id:16;
104 uint32_t relaxed_ordering_write:1;
105 uint32_t relaxed_ordering_read:1;
106 uint32_t access_register_user:1;
107 uint32_t wqe_index_ignore:1;
108 uint32_t cross_channel:1;
109 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
110 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
111 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
112 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
113 uint32_t scatter_fcs_w_decap_disable:1;
114 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
115 uint32_t regex:1;
116 uint32_t regexp_num_of_engines;
117 uint32_t log_max_ft_sampler_num:8;
123 uint32_t wq_type:4;
124 uint32_t wq_signature:1;
125 uint32_t end_padding_mode:2;
126 uint32_t cd_slave:1;
127 uint32_t hds_skip_first_sge:1;
128 uint32_t log2_hds_buf_size:3;
129 uint32_t page_offset:5;
130 uint32_t lwm:16;
131 uint32_t pd:24;
132 uint32_t uar_page:24;
134 uint32_t hw_counter;
135 uint32_t sw_counter;
136 uint32_t log_wq_stride:4;
137 uint32_t log_wq_pg_sz:5;
138 uint32_t log_wq_sz:5;
139 uint32_t dbr_umem_valid:1;
140 uint32_t wq_umem_valid:1;
141 uint32_t log_hairpin_num_packets:5;
142 uint32_t log_hairpin_data_sz:5;
143 uint32_t single_wqe_log_num_of_strides:4;
144 uint32_t two_byte_shift_en:1;
145 uint32_t single_stride_log_num_of_bytes:3;
146 uint32_t dbr_umem_id;
147 uint32_t wq_umem_id;
153 uint32_t rlky:1;
154 uint32_t delay_drop_en:1;
155 uint32_t scatter_fcs:1;
156 uint32_t vsd:1;
157 uint32_t mem_rq_type:4;
158 uint32_t state:4;
159 uint32_t flush_in_error_en:1;
160 uint32_t hairpin:1;
161 uint32_t user_index:24;
162 uint32_t cqn:24;
163 uint32_t counter_set_id:8;
164 uint32_t rmpn:24;
170 uint32_t rqn:24;
171 uint32_t rq_state:4; /* Current RQ state. */
172 uint32_t state:4; /* Required RQ state. */
173 uint32_t scatter_fcs:1;
174 uint32_t vsd:1;
175 uint32_t counter_set_id:8;
176 uint32_t hairpin_peer_sq:24;
177 uint32_t hairpin_peer_vhca:16;
179 uint32_t lwm:16; /* Contained WQ lwm. */
183 uint32_t l3_prot_type:1;
184 uint32_t l4_prot_type:1;
185 uint32_t selected_fields:30;
190 uint32_t disp_type:4;
191 uint32_t lro_timeout_period_usecs:16;
192 uint32_t lro_enable_mask:4;
193 uint32_t lro_max_msg_sz:8;
194 uint32_t inline_rqn:24;
195 uint32_t rx_hash_symmetric:1;
196 uint32_t tunneled_offload_en:1;
197 uint32_t indirect_table:24;
198 uint32_t rx_hash_fn:4;
199 uint32_t self_lb_block:2;
200 uint32_t transport_domain:24;
208 uint32_t tirn:24;
216 uint32_t rqt_max_size:16;
217 uint32_t rqt_actual_size:16;
218 uint32_t rq_list[];
223 uint32_t strict_lag_tx_port_affinity:1;
224 uint32_t tls_en:1;
225 uint32_t lag_tx_port_affinity:4;
226 uint32_t prio:4;
227 uint32_t transport_domain:24;
232 uint32_t rlky:1;
233 uint32_t cd_master:1;
234 uint32_t fre:1;
235 uint32_t flush_in_error_en:1;
236 uint32_t allow_multi_pkt_send_wqe:1;
237 uint32_t min_wqe_inline_mode:3;
238 uint32_t state:4;
239 uint32_t reg_umr:1;
240 uint32_t allow_swp:1;
241 uint32_t hairpin:1;
242 uint32_t non_wire:1;
243 uint32_t static_sq_wq:1;
244 uint32_t user_index:24;
245 uint32_t cqn:24;
246 uint32_t packet_pacing_rate_limit_index:16;
247 uint32_t tis_lst_sz:16;
248 uint32_t tis_num:24;
254 uint32_t sq_state:4;
255 uint32_t state:4;
256 uint32_t hairpin_peer_rq:24;
257 uint32_t hairpin_peer_vhca:16;
263 uint32_t q_umem_valid:1;
264 uint32_t db_umem_valid:1;
265 uint32_t use_first_only:1;
266 uint32_t overrun_ignore:1;
267 uint32_t cqe_comp_en:1;
268 uint32_t mini_cqe_res_format:2;
269 uint32_t mini_cqe_res_format_ext:2;
270 uint32_t cqe_size:3;
271 uint32_t log_cq_size:5;
272 uint32_t log_page_size:5;
273 uint32_t uar_page_id;
274 uint32_t q_umem_id;
276 uint32_t db_umem_id;
278 uint32_t eqn;
287 uint32_t pd:24;
288 uint32_t virtio_version_1_0:1;
289 uint32_t tso_ipv4:1;
290 uint32_t tso_ipv6:1;
291 uint32_t tx_csum:1;
292 uint32_t rx_csum:1;
293 uint32_t event_mode:3;
294 uint32_t state:4;
295 uint32_t dirty_bitmap_dump_enable:1;
296 uint32_t dirty_bitmap_mkey;
297 uint32_t dirty_bitmap_size;
298 uint32_t mkey;
299 uint32_t qp_id;
300 uint32_t queue_index;
301 uint32_t tis_id;
302 uint32_t counters_obj_id;
309 uint32_t id;
310 uint32_t size;
318 uint32_t pd:24;
319 uint32_t uar_index:24;
320 uint32_t cqn:24;
321 uint32_t log_page_size:5;
322 uint32_t rq_size:17; /* Must be power of 2. */
323 uint32_t log_rq_stride:3;
324 uint32_t sq_size:17; /* Must be power of 2. */
325 uint32_t dbr_umem_valid:1;
326 uint32_t dbr_umem_id;
328 uint32_t wq_umem_id;
335 uint32_t error_cqes;
336 uint32_t bad_desc_errors;
337 uint32_t exceed_max_chain;
338 uint32_t invalid_buffer;
346 uint32_t flow_match_sample_en:1;
347 uint32_t flow_match_sample_field_offset:16;
348 uint32_t flow_match_sample_offset_mode:4;
349 uint32_t flow_match_sample_field_offset_mask;
350 uint32_t flow_match_sample_field_offset_shift:4;
351 uint32_t flow_match_sample_field_base_offset:8;
352 uint32_t flow_match_sample_tunnel_mode:3;
353 uint32_t flow_match_sample_field_id;
358 uint32_t compare_condition_value:16;
359 uint32_t start_inner_tunnel:1;
360 uint32_t arc_parse_graph_node:8;
361 uint32_t parse_graph_node_handle;
372 uint32_t modify_field_select;
373 uint32_t header_length_mode:4;
374 uint32_t header_length_base_value:16;
375 uint32_t header_length_field_shift:4;
376 uint32_t header_length_field_offset:16;
377 uint32_t header_length_field_mask;
379 uint32_t next_header_field_offset:16;
380 uint32_t next_header_field_size:5;
389 uint32_t bulk_sz);
394 int clear, uint32_t n_counters,
396 uint32_t mkey, void *addr,
408 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
409 uint32_t *tis_td);
454 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
463 uint32_t ids[], uint32_t num);
471 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
501 uint32_t pd);