Lines Matching refs:uint32_t
80 uint32_t mac_addr_l; /**< Lower 32 bits of 48-bit MAC address */
81 uint32_t mac_addr_u; /**< Upper 16 bits of 48-bit MAC address */
86 uint32_t res0000[2];
87 uint32_t command_config; /**< 0x008 Ctrl and cfg */
89 uint32_t maxfrm; /**< 0x014 Max frame length */
90 uint32_t res0018[5];
91 uint32_t hashtable_ctrl; /**< 0x02C Hash table control */
92 uint32_t res0030[4];
93 uint32_t ievent; /**< 0x040 Interrupt event */
94 uint32_t tx_ipg_length;
96 uint32_t res0048;
97 uint32_t imask; /**< 0x04C Interrupt mask */
98 uint32_t res0050;
99 uint32_t pause_quanta[4]; /**< 0x054 Pause quanta */
100 uint32_t pause_thresh[4]; /**< 0x064 Pause quanta threshold */
101 uint32_t rx_pause_status; /**< 0x074 Receive pause status */
102 uint32_t res0078[2];
105 uint32_t lpwake_timer;
107 uint32_t sleep_timer;
109 uint32_t res00c0[8];
110 uint32_t statn_config;
112 uint32_t res00e4[7];
114 uint32_t reoct_l; /**<Rx Eth Octets Counter */
115 uint32_t reoct_u;
116 uint32_t roct_l; /**<Rx Octet Counters */
117 uint32_t roct_u;
118 uint32_t raln_l; /**<Rx Alignment Error Counter */
119 uint32_t raln_u;
120 uint32_t rxpf_l; /**<Rx valid Pause Frame */
121 uint32_t rxpf_u;
122 uint32_t rfrm_l; /**<Rx Frame counter */
123 uint32_t rfrm_u;
124 uint32_t rfcs_l; /**<Rx frame check seq error */
125 uint32_t rfcs_u;
126 uint32_t rvlan_l; /**<Rx Vlan Frame Counter */
127 uint32_t rvlan_u;
128 uint32_t rerr_l; /**<Rx Frame error */
129 uint32_t rerr_u;
130 uint32_t ruca_l; /**<Rx Unicast */
131 uint32_t ruca_u;
132 uint32_t rmca_l; /**<Rx Multicast */
133 uint32_t rmca_u;
134 uint32_t rbca_l; /**<Rx Broadcast */
135 uint32_t rbca_u;
136 uint32_t rdrp_l; /**<Rx Dropper Packet */
137 uint32_t rdrp_u;
138 uint32_t rpkt_l; /**<Rx packet */
139 uint32_t rpkt_u;
140 uint32_t rund_l; /**<Rx undersized packets */
141 uint32_t rund_u;
142 uint32_t r64_l; /**<Rx 64 byte */
143 uint32_t r64_u;
144 uint32_t r127_l;
145 uint32_t r127_u;
146 uint32_t r255_l;
147 uint32_t r255_u;
148 uint32_t r511_l;
149 uint32_t r511_u;
150 uint32_t r1023_l;
151 uint32_t r1023_u;
152 uint32_t r1518_l;
153 uint32_t r1518_u;
154 uint32_t r1519x_l;
155 uint32_t r1519x_u;
156 uint32_t rovr_l; /**<Rx oversized but good */
157 uint32_t rovr_u;
158 uint32_t rjbr_l; /**<Rx oversized with bad csum */
159 uint32_t rjbr_u;
160 uint32_t rfrg_l; /**<Rx fragment Packet */
161 uint32_t rfrg_u;
162 uint32_t rcnp_l; /**<Rx control packets (0x8808 */
163 uint32_t rcnp_u;
164 uint32_t rdrntp_l; /**<Rx dropped due to FIFO overflow */
165 uint32_t rdrntp_u;
166 uint32_t res01d0[12];
168 uint32_t teoct_l; /**<Tx eth octets */
169 uint32_t teoct_u;
170 uint32_t toct_l; /**<Tx Octets */
171 uint32_t toct_u;
172 uint32_t res0210[2];
173 uint32_t txpf_l; /**<Tx valid pause frame */
174 uint32_t txpf_u;
175 uint32_t tfrm_l; /**<Tx frame counter */
176 uint32_t tfrm_u;
177 uint32_t tfcs_l; /**<Tx FCS error */
178 uint32_t tfcs_u;
179 uint32_t tvlan_l; /**<Tx Vlan Frame */
180 uint32_t tvlan_u;
181 uint32_t terr_l; /**<Tx frame error */
182 uint32_t terr_u;
183 uint32_t tuca_l; /**<Tx Unicast */
184 uint32_t tuca_u;
185 uint32_t tmca_l; /**<Tx Multicast */
186 uint32_t tmca_u;
187 uint32_t tbca_l; /**<Tx Broadcast */
188 uint32_t tbca_u;
189 uint32_t res0258[2];
190 uint32_t tpkt_l; /**<Tx Packet */
191 uint32_t tpkt_u;
192 uint32_t tund_l; /**<Tx Undersized */
193 uint32_t tund_u;
194 uint32_t t64_l;
195 uint32_t t64_u;
196 uint32_t t127_l;
197 uint32_t t127_u;
198 uint32_t t255_l;
199 uint32_t t255_u;
200 uint32_t t511_l;
201 uint32_t t511_u;
202 uint32_t t1023_l;
203 uint32_t t1023_u;
204 uint32_t t1518_l;
205 uint32_t t1518_u;
206 uint32_t t1519x_l;
207 uint32_t t1519x_u;
208 uint32_t res02a8[6];
209 uint32_t tcnp_l; /**<Tx Control Packet type - 0x8808 */
210 uint32_t tcnp_u;
211 uint32_t res02c8[14];
213 uint32_t if_mode; /**< 0x300 Interface Mode Control */
214 uint32_t if_status; /**< 0x304 Interface Status */
215 uint32_t res0308[14];
217 uint32_t hg_config; /**< 0x340 Control and cfg */
218 uint32_t res0344[3];
219 uint32_t hg_pause_quanta; /**< 0x350 Pause quanta */
220 uint32_t res0354[3];
221 uint32_t hg_pause_thresh; /**< 0x360 Pause quanta threshold */
222 uint32_t res0364[3];
223 uint32_t hgrx_pause_status; /**< 0x370 Receive pause status */
224 uint32_t hg_fifos_status; /**< 0x374 fifos status */
225 uint32_t rhm; /**< 0x378 rx messages counter */
226 uint32_t thm; /**< 0x37C tx messages counter */
232 uint32_t fmbm_rcfg; /**< Rx Configuration */
233 uint32_t fmbm_rst; /**< Rx Status */
234 uint32_t fmbm_rda; /**< Rx DMA attributes*/
235 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
236 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
237 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
238 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
239 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
240 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
241 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
242 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
243 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
244 uint32_t fmbm_rpp; /**< Rx Policer Profile */
245 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
246 uint32_t fmbm_reth; /**< Rx Excessive Threshold */
247 uint32_t reserved003c[1]; /**< (0x03C 0x03F) */
248 uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
250 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
251 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
252 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
253 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
254 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
255 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
256 uint32_t fmbm_rcmne;
258 uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */
259 uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
261 uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
263 uint32_t reserved0130[8];
265 uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
267 uint32_t fmbm_mpd; /**< BM Pool Depletion */
268 uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */
269 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
270 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
271 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
272 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
273 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
274 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/
275 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
276 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/
277 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
278 uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */
279 uint32_t fmbm_rpc; /**< Rx Performance Counters*/
280 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
281 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
282 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
283 uint32_t fmbm_rrquc;
285 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
286 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
287 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
288 uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */
289 uint32_t fmbm_rdbg; /**< Rx Debug-*/
293 uint32_t fmqm_pnc; /**< PortID n Configuration Register */
294 uint32_t fmqm_pns; /**< PortID n Status Register */
295 uint32_t fmqm_pnts; /**< PortID n Task Status Register */
296 uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */
297 uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
298 uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */
299 uint32_t reserved024[2]; /**< 0xn024 - 0x02B */
300 uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
301 uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
302 uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */
303 uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */
304 uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
334 uint32_t fqid_rx_def;
335 uint32_t fqid_rx_err;
336 uint32_t fqid_tx_err;
337 uint32_t fqid_tx_confirm;
348 uint32_t bpid;