Lines Matching refs:RTE_ACL_IPV4VLAN_DST_FIELD

97 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;  in acl_ipv4vlan_convert_rule()
107 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;  in acl_ipv4vlan_convert_rule()
196 			.field_index = RTE_ACL_IPV4VLAN_DST_FIELD,  in acl_ipv4vlan_config()
225 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =  in acl_ipv4vlan_config()
598 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;  in convert_rule()
608 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;  in convert_rule()
629 	v = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32;  in convert_rule_1()
630 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 =  in convert_rule_1()
653 	mask = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32;  in convert_rule_2()
655 	lo = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 & mask;  in convert_rule_2()
657 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = lo;  in convert_rule_2()
658 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = hi;  in convert_rule_2()
697 		ro->field[RTE_ACL_IPV4VLAN_DST_FIELD];  in convert_rule_4()
699 	ro->field[RTE_ACL_IPV4VLAN_DST_FIELD] = t;  in convert_rule_4()
736 			.field_index = RTE_ACL_IPV4VLAN_DST_FIELD,  in ipv4vlan_config()
765 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =  in ipv4vlan_config()
814 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = RTE_ACL_FIELD_TYPE_BITMASK;  in convert_config_1()
825 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = RTE_ACL_FIELD_TYPE_RANGE;  in convert_config_2()
875 		cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD];  in convert_config_4()
879 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = t.type;  in convert_config_4()
880 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].size = t.size;  in convert_config_4()
881 	cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset = t.offset;  in convert_config_4()