192 	struct txgbe_hic_read_shadow_ram command;  in txgbe_hic_sr_read()  local
199 	memset(&command, 0, sizeof(command));  in txgbe_hic_sr_read()
200 	command.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;  in txgbe_hic_sr_read()
201 	command.hdr.req.buf_lenh = 0;  in txgbe_hic_sr_read()
202 	command.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;  in txgbe_hic_sr_read()
203 	command.hdr.req.checksum = FW_DEFAULT_CHECKSUM;  in txgbe_hic_sr_read()
204 	command.address = cpu_to_be32(addr);  in txgbe_hic_sr_read()
205 	command.length = cpu_to_be16(len);  in txgbe_hic_sr_read()
207 	err = txgbe_hic_unlocked(hw, (u32 *)&command,  in txgbe_hic_sr_read()
208 			sizeof(command), TXGBE_HI_COMMAND_TIMEOUT);  in txgbe_hic_sr_read()
235 	struct txgbe_hic_write_shadow_ram command;  in txgbe_hic_sr_write()  local
242 	memset(&command, 0, sizeof(command));  in txgbe_hic_sr_write()
243 	command.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;  in txgbe_hic_sr_write()
244 	command.hdr.req.buf_lenh = 0;  in txgbe_hic_sr_write()
245 	command.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;  in txgbe_hic_sr_write()
246 	command.hdr.req.checksum = FW_DEFAULT_CHECKSUM;  in txgbe_hic_sr_write()
247 	command.address = cpu_to_be32(addr);  in txgbe_hic_sr_write()
248 	command.length = cpu_to_be16(len);  in txgbe_hic_sr_write()
261 	UNREFERENCED_PARAMETER(&command);  in txgbe_hic_sr_write()