Lines Matching refs:info
236 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) in mlx5_set_default_params() argument
241 info->default_rxportconf.ring_size = 256; in mlx5_set_default_params()
242 info->default_txportconf.ring_size = 256; in mlx5_set_default_params()
243 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; in mlx5_set_default_params()
244 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; in mlx5_set_default_params()
247 info->default_rxportconf.nb_queues = 16; in mlx5_set_default_params()
248 info->default_txportconf.nb_queues = 16; in mlx5_set_default_params()
252 info->default_rxportconf.ring_size = 2048; in mlx5_set_default_params()
253 info->default_txportconf.ring_size = 2048; in mlx5_set_default_params()
256 info->default_rxportconf.nb_queues = 8; in mlx5_set_default_params()
257 info->default_txportconf.nb_queues = 8; in mlx5_set_default_params()
261 info->default_rxportconf.ring_size = 4096; in mlx5_set_default_params()
262 info->default_txportconf.ring_size = 4096; in mlx5_set_default_params()
276 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) in mlx5_set_txlimit_params() argument
299 info->tx_desc_lim.nb_seg_max = nb_max; in mlx5_set_txlimit_params()
300 info->tx_desc_lim.nb_mtu_seg_max = nb_max; in mlx5_set_txlimit_params()
312 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) in mlx5_dev_infos_get() argument
318 info->min_rx_bufsize = 32; in mlx5_dev_infos_get()
319 info->max_rx_pktlen = 65536; in mlx5_dev_infos_get()
320 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; in mlx5_dev_infos_get()
328 info->max_rx_queues = max; in mlx5_dev_infos_get()
329 info->max_tx_queues = max; in mlx5_dev_infos_get()
330 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; in mlx5_dev_infos_get()
331 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); in mlx5_dev_infos_get()
332 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; in mlx5_dev_infos_get()
333 info->rx_seg_capa.multi_pools = !priv->config.mprq.enabled; in mlx5_dev_infos_get()
334 info->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled; in mlx5_dev_infos_get()
335 info->rx_seg_capa.offset_align_log2 = 0; in mlx5_dev_infos_get()
336 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | in mlx5_dev_infos_get()
337 info->rx_queue_offload_capa); in mlx5_dev_infos_get()
338 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); in mlx5_dev_infos_get()
339 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; in mlx5_dev_infos_get()
340 info->if_index = mlx5_ifindex(dev); in mlx5_dev_infos_get()
341 info->reta_size = priv->reta_idx_n ? in mlx5_dev_infos_get()
343 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; in mlx5_dev_infos_get()
344 info->speed_capa = priv->link_speed_capa; in mlx5_dev_infos_get()
345 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; in mlx5_dev_infos_get()
346 mlx5_set_default_params(dev, info); in mlx5_dev_infos_get()
347 mlx5_set_txlimit_params(dev, info); in mlx5_dev_infos_get()
350 info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; in mlx5_dev_infos_get()
351 info->switch_info.name = dev->data->name; in mlx5_dev_infos_get()
352 info->switch_info.domain_id = priv->domain_id; in mlx5_dev_infos_get()
353 info->switch_info.port_id = priv->representor_id; in mlx5_dev_infos_get()
354 info->switch_info.rx_domain = 0; /* No sub Rx domains. */ in mlx5_dev_infos_get()
371 info->switch_info.name = opriv->dev_data->name; in mlx5_dev_infos_get()
395 mlx5_representor_id_encode(const struct mlx5_switch_info *info, in mlx5_representor_id_encode() argument
399 uint16_t repr = info->port_name; in mlx5_representor_id_encode()
401 if (info->representor == 0) in mlx5_representor_id_encode()
403 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF) in mlx5_representor_id_encode()
405 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) { in mlx5_representor_id_encode()
409 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr); in mlx5_representor_id_encode()
430 struct rte_eth_representor_info *info) in mlx5_representor_info_get() argument
438 if (info == NULL) in mlx5_representor_info_get()
442 if ((uint32_t)n_entries > info->nb_ranges_alloc) in mlx5_representor_info_get()
443 n_entries = info->nb_ranges_alloc; in mlx5_representor_info_get()
445 info->controller = 0; in mlx5_representor_info_get()
446 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0; in mlx5_representor_info_get()
449 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; in mlx5_representor_info_get()
450 info->ranges[i].controller = 0; in mlx5_representor_info_get()
451 info->ranges[i].pf = pf; in mlx5_representor_info_get()
452 info->ranges[i].vf = 0; in mlx5_representor_info_get()
453 info->ranges[i].id_base = in mlx5_representor_info_get()
454 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); in mlx5_representor_info_get()
455 info->ranges[i].id_end = in mlx5_representor_info_get()
456 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
457 snprintf(info->ranges[i].name, in mlx5_representor_info_get()
458 sizeof(info->ranges[i].name), "pf%dvf", pf); in mlx5_representor_info_get()
463 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; in mlx5_representor_info_get()
464 info->ranges[i].controller = 0; in mlx5_representor_info_get()
465 info->ranges[i].pf = pf; in mlx5_representor_info_get()
466 info->ranges[i].vf = UINT16_MAX; in mlx5_representor_info_get()
467 info->ranges[i].id_base = in mlx5_representor_info_get()
468 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
469 info->ranges[i].id_end = in mlx5_representor_info_get()
470 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
471 snprintf(info->ranges[i].name, in mlx5_representor_info_get()
472 sizeof(info->ranges[i].name), "pf%dvf", pf); in mlx5_representor_info_get()
477 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; in mlx5_representor_info_get()
478 info->ranges[i].controller = 0; in mlx5_representor_info_get()
479 info->ranges[i].pf = pf; in mlx5_representor_info_get()
480 info->ranges[i].vf = 0; in mlx5_representor_info_get()
481 info->ranges[i].id_base = in mlx5_representor_info_get()
482 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); in mlx5_representor_info_get()
483 info->ranges[i].id_end = in mlx5_representor_info_get()
484 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
485 snprintf(info->ranges[i].name, in mlx5_representor_info_get()
486 sizeof(info->ranges[i].name), "pf%dsf", pf); in mlx5_representor_info_get()
491 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; in mlx5_representor_info_get()
492 info->ranges[i].controller = 0; in mlx5_representor_info_get()
493 info->ranges[i].pf = pf; in mlx5_representor_info_get()
494 info->ranges[i].vf = UINT16_MAX; in mlx5_representor_info_get()
495 info->ranges[i].id_base = in mlx5_representor_info_get()
496 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
497 info->ranges[i].id_end = in mlx5_representor_info_get()
498 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); in mlx5_representor_info_get()
499 snprintf(info->ranges[i].name, in mlx5_representor_info_get()
500 sizeof(info->ranges[i].name), "pf%dsf", pf); in mlx5_representor_info_get()
505 info->nb_ranges = i; in mlx5_representor_info_get()