730 	ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);  in i40e_write_global_rx_ctl()
1219 	glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);  in i40e_init_filter_invalidation()
4367 				lut_dw[i] = i40e_read_rx_ctl(hw, reg);  in i40e_get_rss_lut()
7636 				key_dw[i] = i40e_read_rx_ctl(hw, reg);  in i40e_get_rss_key()
7643 				key_dw[i] = i40e_read_rx_ctl(hw, reg);  in i40e_get_rss_key()
7681 	hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));  in i40e_dev_rss_hash_update()
7682 	hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;  in i40e_dev_rss_hash_update()
7713 	hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));  in i40e_dev_rss_hash_conf_get()
7714 	hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;  in i40e_dev_rss_hash_conf_get()
8790 	reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);  in i40e_pf_global_rss_reset()
8801 			pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));  in i40e_pf_global_rss_reset()
8827 		reg_val = i40e_read_rx_ctl(hw, reg);  in i40e_pf_global_rss_reset()
8987 	uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);  in i40e_set_symmetric_hash_enable_per_port()
9440 		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));  in i40e_get_inset_field_offset()
9549 	uint32_t reg = i40e_read_rx_ctl(hw, addr);  in i40e_check_write_reg()
9555 		    (uint32_t)i40e_read_rx_ctl(hw, addr));  in i40e_check_write_reg()
9561 	uint32_t reg = i40e_read_rx_ctl(hw, addr);  in i40e_check_write_global_reg()
9572 			    (uint32_t)i40e_read_rx_ctl(hw, addr));  in i40e_check_write_global_reg()
9666 		pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));  in i40e_set_hash_inset()
9670 		inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));  in i40e_set_hash_inset()
9672 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));  in i40e_set_hash_inset()
11163 					i40e_read_rx_ctl(hw, reg_offset);  in i40e_get_regs()